Patents by Inventor Jaime Cummins

Jaime Cummins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220147809
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A compiler can convert a description of an artificial neural network into a compiler output through optimization and/or selection of hardware options of the integrated circuit device. The compiler output can include parameters of the artificial neural network, instructions executable by processing units of the Deep Learning Accelerator to generate an output of the artificial neural network responsive to an input to the artificial neural network, and hardware options to be stored in registers connected to control hardware configurations of the processing units.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Inventors: Aliasger Tayeb Zaidy, Marko Vitez, Eugenio Culurciello, Jaime Cummins, Andre Xian Ming Chang
  • Publication number: 20220147810
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Inventors: Aliasger Tayeb Zaidy, Marko Vitez, Eugenio Culurciello, Jaime Cummins, Andre Xian Ming Chang
  • Publication number: 20220147808
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can convert a description of an artificial neural network into a generic result of compilation according to a specification of a generic Deep Learning Accelerator and then map the first result of compilation into a platform-specific result according to a specification of a specific hardware platform of Deep Learning Accelerators. The platform-specific result can be stored into the RAM of the integrated circuit device to enable the integrated circuit device to autonomously perform the computation of the artificial neural network in generating an output in response to an input to the artificial neural network.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Inventors: Andre Xian Ming Chang, Aliasger Tayeb Zaidy, Eugenio Culurciello, Jaime Cummins, Marko Vitez
  • Publication number: 20220147811
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can identify a plurality of portions of an artificial neural network for implementation on a plurality of such integrated circuit devices respectively. The compiler converts a description of the artificial neural network into a plurality of compiler outputs executable on the plurality of devices to generate an output of the artificial neural network response to an input to the artificial neural network. Intermediate results are communicated among the devices in generating the output of the artificial neural network.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Inventors: Jaime Cummins, Marko Vitez, Eugenio Culurciello, Andre Xian Ming Chang, Aliasger Tayeb Zaidy
  • Patent number: 11284394
    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Jaime Cummins, Tamara Schmitz, Jeremy Chritz
  • Publication number: 20220060226
    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of an autocorrelation calculator. An electronic device including an autocorrelation calculator may be configured to calculate an autocorrelation matrix including an autocorrelation of symbols indicative of a first narrowband Internet of Things (IoT) transmission and a second narrowband IoT transmission. The electronic device may calculate the autocorrelation matrix based on a stored autocorrelation matrix and the autocorrelation of symbols indicative of the first narrowband IoT transmission and symbols indicative of the second narrowband IoT transmission. The stored autocorrelation matrix may represent another received signal at a different time period than a time period of the first and second narrowband IoT transmission.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: FA-LONG LUO, TAMARA SCHMITZ, JEREMY CHRITZ, JAIME CUMMINS
  • Publication number: 20220014217
    Abstract: Systems, methods, and apparatuses for wireless communication are described. Input data for in-phase branch/quadrature branch (I/Q) imbalance or mismatch may be compensated for or non-linear power amplifier noise may be used to generate compensated input data. In some examples, a transmitter may be configured to transmit communications signaling via a first antenna, the transmitter including a filter configured for digital mismatch correction; a receiver may be configured to receive communications signaling via a second antenna; and a switch may be configured to selectively activate a first switch path to couple the transmitter and the first antenna and a second switch path to couple the receiver and the transmitter to provide communications signaling received via the transmitter as feedback for the filter through the receiver.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: FA-LONG LUO, JAIME CUMMINS, TAMARA SCHMITZ, JEREMY CHRITZ
  • Patent number: 11206050
    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator that compensates for the self-interference noise generated by power amplifiers at harmonic frequencies of a respective wireless receiver. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate the adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Jaime Cummins, Tamara Schmitz, Jeremy Chritz
  • Patent number: 11201646
    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of an autocorrelation calculator. An electronic device including an autocorrelation calculator may be configured to calculate an autocorrelation matrix including an autocorrelation of symbols indicative of a first radio frequency (“RF”) signal and a second RF signal. The electronic device may calculate the autocorrelation matrix based on a stored autocorrelation matrix and the autocorrelation of symbols indicative of the first RF signal and symbols indicative of the second RF signal. The stored autocorrelation matrix may represent another received signal at a different time period than a time period of the first and second RF signals. Examples of the systems and methods may facilitate the processing of data for wireless and may utilize less memory space than a device than a scheme that stores and calculates autocorrelation from a large dataset computed from various time points.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: December 14, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fa-Long Luo, Tamara Schmitz, Jeremy Chritz, Jaime Cummins
  • Publication number: 20210367822
    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to the wireless protocol in the RF wireless domain. A computing device may be trained to generate coefficient data based on the operations of a wireless transceiver such that mixing input data using the coefficient data generates an approximation of the output data, as if it were processed by the wireless transceiver. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: JEREMY CHRITZ, TAMARA SCHMITZ, FA-LONG LUO, JAIME CUMMINS
  • Publication number: 20210367823
    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. The processing mode selection may include a single processing mode, a multi-processing mode, or a full processing mode. The processing mode selection may be associated with an aspect of a wireless protocol. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fa-Long LUO, Jaime CUMMINS, Jeremy CHRITZ, Tamara SCHMITZ
  • Patent number: 11159188
    Abstract: Examples described herein include methods, devices, and systems which may compensate input data for non-linear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a coefficient calculator. The coefficient calculator may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to a coefficient calculator. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Jeremy Chritz, Jaime Cummins, Tamara Schmitz
  • Publication number: 20210328631
    Abstract: Examples described herein include systems and methods, including wireless devices and systems with neuron calculators that may perform one or more functionalities of a wireless transceiver. The neuron calculator calculates output signals that may be implemented, for example, using accumulation units that sum the multiplicative processing results of ordered sets from ordered neurons with connection weights for each connection between an ordered neuron and outputs of the neuron calculator. The ordered sets may be a combination of some input signals, with the number of signals determined by an order of the neuron. Accordingly, a kth-order neuron may include an ordered set comprising product values of k input signals, where the input signals are selected from a set of k-combinations with repetition. As an example in a wireless transceiver, the neuron calculator may perform channel estimation as a channel estimation processing component of the receiver portion of a wireless transceiver.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fa-Long Luo, Jaime Cummins, Tamara Schmitz, Jeremy Chritz
  • Publication number: 20210319821
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to perform at least computations on matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; and an interface to a memory controller. The interface may be configured to facilitate access to the random access memory by the memory controller. In response to an indication provided in the random access memory, the Deep Learning Accelerator may execute the instructions to apply input that is stored in the random access memory to the Artificial Neural Network, generate output from the Artificial Neural Network, and store the output in the random access memory.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Poorna Kale, Jaime Cummins
  • Publication number: 20210319823
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Poorna Kale, Jaime Cummins
  • Publication number: 20210319822
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to a direct memory access controller. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the direct memory access controller may concurrently load next input into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Poorna Kale, Jaime Cummins
  • Publication number: 20210320967
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be implemented using an integrated circuit device having: a Deep Learning Accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of a server application executable by a Central Processing Unit; and an interface to a communication device on a computer network. The Central Processing Unit may be part of the integrated circuit device, or be connected to the integrated circuit device. The server application may be configured to provide services over the computer network based on output of the Artificial Neural Network and input received from one or more local devices via a bus, or a wired or wireless local area network.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Poorna Kale, Jaime Cummins
  • Publication number: 20210318871
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be configured on a local area network to receive sensor data of a person, such as a patient in a hospital or care center. The edge server may be implemented using an integrated circuit device having: a Deep Learning Accelerator configured to execute instructions with matrix operands; and random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of a server application executable by a Central Processing Unit. An output of the Artificial Neural Network with the sensor data as input may identify a condition of the person, based on which the server application generates an alert, causing a central server to request intervention of the detected or predicted condition for the person.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Poorna Kale, Jaime Cummins
  • Publication number: 20210319305
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured with: a Central Processing Unit, a Deep Learning Accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of an application executable by the Central Processing Unit; one or connections among the random access memory, the Deep Learning Accelerator and the Central Processing Unit; and an input/output interface to an external peripheral bus. While the Deep Learning Accelerator is executing the first instructions to convert sensor data according to the Artificial Neural Network to inference results, the Central Processing Unit may execute the application that uses inference results from the Artificial Neural Network.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Poorna Kale, Jaime Cummins
  • Patent number: 11139845
    Abstract: Systems, methods, and apparatuses for wireless communication are described. Input data for in-phase branch/quadrature branch (I/Q) imbalance or mismatch may be compensated for or non-linear power amplifier noise may be used to generate compensated input data. In some examples, a transmitter may be configured to transmit communications signaling via a first antenna, the transmitter including a filter configured for digital mismatch correction; a receiver may be configured to receive communications signaling via a second antenna; and a switch may be configured to selectively activate a first switch path to couple the transmitter and the first antenna and a second switch path to couple the receiver and the transmitter to provide communications signaling received via the transmitter as feedback for the filter through the receiver.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: October 5, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fa-Long Luo, Jaime Cummins, Tamara Schmitz, Jeremy Chritz