Abstract: A low-voltage supply low-power variable gain amplifier is shown that includes an input control circuit for receiving input signals, a variable gain amplifier (VGA) coupled to the input control circuit, and a circuit output terminal. A differential transconductor is interposed between the input control circuit and the VGA. The VGA amplification of the differential transconductor output is controlled by a gain control voltage signal. A differential amplifier is interposed between the input control circuit and the differential transconductor, where the differential amplifier receives and amplifies the input signal to produce an amplified input signal. An output filter is interposed between the VGA and the circuit output terminal.

Abstract: A mixer contains a multiplier circuit that includes MOS transistors configured as a Gilbert multiplier cell without gain resistors such that a first and a second node are directly coupled to a folded cascode output stage. The mixer receives a differential radio frequency (RF) signal and a differential local oscillator (LO) signal, and it generates, at the first and second nodes, a differential intermediate frequency (IF) signal. The mixer further includes output and gain/filter stages coupled to the multiplier circuit. The output stage exhibits a low input impedance and a high output impedance, and it generates an output stage differential current approximately equal to the differential current of the IF differential signal. The gain/filter stage both controls conversion gain of the mixer, and it filters the high frequency components generated by said multiplier circuit. A capacitor, implemented as the gain/filter stage, and a folded-cascode circuit for the output stage are disclosed.

Abstract: A transceiver integrated circuit including a transmitter section having a phase-locked loop with an oscillator to provide an output at a predetermined transmission frequency, and a receiver section having a phase-locked loop with an oscillator used to provide a recovered clock from an incoming data signal. In a second mode when no incoming data is being received, the receiver oscillator is controlled in accordance with the transmitter oscillator to operate the receiver oscillator at the expected frequency of future data. Therefore, when data is received, the receiver oscillator is at the same approximate frequency as the incoming data thereby enabling fast acquisition by merely adjusting the phase of the receiver oscillator to the incoming data.

Abstract: A digitally programmable Bessel filter includes a plurality of serially connected stages or biquads with each biquad including a plurality of programmable operational transconductance amplifiers. The first stage of the filter provides an all pass equal amplitude response. Two stages provide pulse slimming (first and second derivatives of an input pulse), and three stages provides a sixth order Bessel low pass function. The operational transconductance amplifiers are controlled by a fine tuning control signal, and an array of integrating capacitors are selectively controlled by a coarse tuning signal. The fine tuning and coarse tuning signals are generated in a phase locked loop from a reference clock and a reference biquad which receives the reference clock.

Abstract: A high speed clock recovery system that provides a precise 90.degree. phase shift at the incoming NRZ data rate by using a series of differential inverters and controlling their delays in accordance with the corresponding delays of differential inverters of a ring oscillator that is part of a phase-locked loop. More particularly, the incoming NRZ data and the phase shifted data are fed to an exclusive OR that provides an output signal including a frequency component of the originating clock of the NRZ data. The phase-locked loop further includes a phase detector which is responsive to the output of the exclusive OR and the ring oscillator. Thus, once the loop locks, the ring oscillator is synchronized to the frequency of the originating clock for the NRZ data. By slaving the differential inverters of the phase shifter and the ring oscillator to the same delays, the phase shifter provides a dynamically adjusted delay of precisely 90.degree. at the originating clock frequency of the incoming NRZ data.

Abstract: A digitally programmable Bessel filter includes a plurality of serially connected stages or biquads with each biquad including a plurality of programmable operational transconductance amplifiers. The first stage of the filter provides an all pass equal amplitude response. Two stages provide pulse slimming (first and second derivatives of an input pulse), and three stages provides a sixth order Bessel low pass function. The operational transconductance amplifiers are controlled by a fine tuning control signal, and an array of integrating capacitors are selectively controlled by a coarse tuning signal. The fine tuning and coarse tuning signals are generated in a phase locked loop from a reference clock and a reference biquad which receives the reference clock.