Patents by Inventor Jaime FERRAGUT MARTINEZ-VARA DE REY

Jaime FERRAGUT MARTINEZ-VARA DE REY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bit processing
    Patent number: 10366741
    Abstract: Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing a
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: July 30, 2019
    Assignee: ARM Limited
    Inventors: Neil Burgess, Nigel John Stephens, Lee Evan Eisen, Jaime Ferragut Martinez-Vara De Rey
  • BIT PROCESSING
    Publication number: 20190088307
    Abstract: Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing a
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Inventors: Neil BURGESS, Nigel John STEPHENS, Lee Evan EISEN, Jaime FERRAGUT MARTINEZ-VARA DE REY