Patents by Inventor Jain-Hon Chen

Jain-Hon Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7135400
    Abstract: A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k?2.9) thereon, a SiC layer over the low-k dielectric layer, and a blocking layer over the SiC layer. The blocking layer is used to prevent unpolymerized precursors diffused out from the low-k dielectric layer from contacting an overlying resist. A bottom anti-reflection coating (BARC) layer is formed on the blocking layer. A resist layer is formed on the BARC layer, the resist layer having an opening to expose a portion of the BARC layer. A damascene structure is formed in the low-k dielectric layer by etching the BARC layer, the blocking layer, the SiC layer, and the low-k dielectric layer through the opening.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: November 14, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Liang Lien, Charlie C J Lee, Chih-Ning Wu, Jain-Hon Chen
  • Publication number: 20050239285
    Abstract: A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k?2.9) thereon, a SiC layer over the low-k dielectric layer, and a blocking layer over the SiC layer. The blocking layer is used to prevent unpolymerized precursors diffused out from the low-k dielectric layer from contacting an overlying resist. A bottom anti-reflection coating (BARC) layer is formed on the blocking layer. A resist layer is formed on the BARC layer, the resist layer having an opening to expose a portion of the BARC layer. A damascene structure is formed in the low-k dielectric layer by etching the BARC layer, the blocking layer, the SiC layer, and the low-k dielectric layer through the opening.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 27, 2005
    Inventors: Wen-Liang Lien, Charlie CJ Lee, Chih-Ning Wu, Jain-Hon Chen
  • Patent number: 6531406
    Abstract: A method of fabricating a shallow trench isolation, which is applicable on a substrate, is described. A pad oxide layer, a silicon oxynitride layer and a patterned photoresist layer are formed on the substrate, wherein a thickness of the silicon oxynitride layer is greater than 800 angstroms. Subsequently, the exposed silicon oxynitride layer is removed by using the photoresist layer as a mask, and the exposed pad oxide layer and a part of the substrate are removed by using the silicon oxynitride layer as a mask to form a shallow trench. An isolating material is then filled into the shallow trench to form a shallow trench isolation.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: March 11, 2003
    Assignee: United Microelectronics Corp.
    Inventor: Jain-Hon Chen
  • Patent number: 6497981
    Abstract: A method of forming a color filter array. A substrate having a passivation layer thereon is provided. A negative color photoresist layer is formed over the passivation layer. A photolithographic exposure process is conducted using a light source with a wavelength less than or equal to 248 nm so that a pattern for forming a color filter array is imprinted on the negative color photoresist layer.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: December 24, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Jain-Hon Chen, Jeenh-Bang Yeh
  • Publication number: 20020127481
    Abstract: A method of forming a color filter array. A substrate having a passivation layer thereon is provided. A negative color photoresist layer is formed over the passivation layer. A photolithographic exposure process is conducted using a light source with a wavelength less than or equal to 248 nm so that a pattern for forming a color filter array is imprinted on the negative color photoresist layer.
    Type: Application
    Filed: March 7, 2001
    Publication date: September 12, 2002
    Inventors: Jain-Hon Chen, Jeenh-Bang Yeh
  • Patent number: 6387785
    Abstract: A lithography and etching process, which is applicable on a substrate, is described. A material layer to be patterned is formed on the substrate, then a silicon oxynitride layer of more than 800 angstroms in thickness is formed over the material layer. Subsequently, a patterned photoresist layer is formed over the silicon oxynitride layer, followed by removing the exposed silicon oxynitride layer by using the photoresist layer as a mask, and removing the exposed material layer by using the patterned silicon oxynitride layer as a mask to form a patterned material layer.
    Type: Grant
    Filed: July 22, 2000
    Date of Patent: May 14, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Jain-Hon Chen
  • Publication number: 20020009865
    Abstract: A lithography and etching process, which is applicable on a substrate, is described. A material layer to be patterned is formed on the substrate, then a silicon oxynitride layer of more than 800 angstroms in thickness is formed over the material layer. Subsequently, a patterned photoresist layer is formed over the silicon oxynitride layer, followed by removing the exposed silicon oxynitride layer by using the photoresist layer as a mask, and removing the exposed material layer by using the patterned silicon oxynitride layer as a mask to form a patterned material layer.
    Type: Application
    Filed: April 30, 2001
    Publication date: January 24, 2002
    Inventor: Jain-Hon Chen
  • Patent number: 6232238
    Abstract: The present invention provides a method for preventing corrosion of a bonding pad resulting from residual polymers on a surface of a semiconductor wafer. The bonding pad is a metallic layer formed on the surface of the semiconductor wafer. The semiconductor wafer comprises an inorganic passivation layer positioned above the bonding pad, and an organic dielectric layer positioned above the inorganic passivation layer. The passivation and dielectric layers comprise a hole etched to the bonding pad. The method uses an organic solution to clean off residual polymers on the surface of the bonding pad inside the hole to prevent corrosion of the bonding pad.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: May 15, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Chun Chang, Jain-Hon Chen
  • Patent number: 6136665
    Abstract: A recess-free buffer layer is formed on a semiconductor substrate having island structures formed thereon. A first buffer layer is formed over the substrate and the island structures. A first reflow process is then performed for reflowing the first buffer layer into spaces between the island structures. A portion of the first buffer layer located outside the spaces is removed. A second buffer layer is formed over the first buffer layer and the island structures. The method can further include a step of performing a second thermal soft-bake process to the second buffer layer. The second buffer layer can also be patterned after the soft-bake process.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: October 24, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Fa Ku, Jain-Hon Chen
  • Patent number: 6025206
    Abstract: A method for detecting defects comprises scanning a clean blank wafer for figuring out the quantity and locations of particles; then, scanning the wafer again after performing coating, exposure, and development processes on the wafer; comparing the two scanning results for figuring out the locations of the defects and calculating quantities of the defects by checking the patterns and colors, and then to obtain the quantities and types of the defects in mechanisms and photoresist respectively.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: February 15, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Jain-Hon Chen, Chi-Fa Ku, Li-Dar Tsai