Abstract: Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.

Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.

Abstract: A system that includes two or more processor circuitry components and a power management circuitry comprising timestamp generator circuitry. In some examples, the timestamp generator circuitry is to generate timestamp values based on a single clock source and provide generated timestamp values to the two or more processor circuitry components. In some examples, the two or more processor circuitry components share timestamp values and the two or more processor circuitry components are to generate performance data associated with a timestamp of the generated timestamp values.

Abstract: Apparatus and method for concurrent performance monitoring. For example, one embodiment of an apparatus comprises: compute hardware logic to concurrently process a number of workloads, the compute hardware logic to be subdivided into a plurality of compute hardware contexts based on the number of workloads; and programmable performance monitoring circuitry to be dynamically partitioned to perform parallel performance monitoring operations to monitor performance of each of the plurality of compute hardware contexts while the number of workloads are concurrently processed, the programmable performance monitoring circuitry to differentiate between performance monitoring data of different compute hardware contexts based on a unique identifier associated with each of the compute hardware contexts.

Abstract: A method implemented in a node to forward data packets via a communication link to another node. The method includes receiving an indication of a resource level associated with one or more ports among the other node's ingress and egress ports. The indication to be received via a side-band communication link coupled to the other node. The method further includes forwarding one or more data packets associated with data to the other node based on the indicated resource level received via the side-band communication link.

Abstract: A method that includes determining a pending data packet count for one or more data packets associated with data to be forwarded from a node to another node on a communication link and then comparing the pending data packet count to a threshold data packet count value. The method further includes forwarding the one or more data packets to the other node at a rate based on the comparison.

Abstract: Method and apparatus to perform cyclic redundancy check computations for error detection are described wherein a first stage includes a first set of computation elements, a first multiplexer and a second multiplexer. A latch is connected to the first stage. A second stage is connected to the latch and the second stage includes a second set of computation elements and a third multiplexer. The first stage and the second stage perform cyclic redundancy check computations for a packet, with the first set of computation elements performing cyclic redundancy check computations for a first set of bytes of input data from the packet, and the second set of computation elements performing cyclic redundancy check computations for a second set of bytes of input data from the packet. Other embodiments are described and claimed.

Abstract: A method implemented in a node to forward data packets via a communication link to another node. The method includes receiving an indication of a resource level associated with one or more ports among the other node's ingress and egress ports. The indication to be received via a side-band communication link coupled to the other node. The method further includes forwarding one or more data packets associated with data to the other node based on the indicated resource level received via the side-band communication link.

Abstract: In a method of allocating a shared resource among a plurality of competing applicants, a share of the resource allocated to one of the applicants is limited on the basis of a current proportion of the resource allocated to the applicant and a total of respective shares of the resource currently allocated to all of the applicants.

Abstract: A method that includes determining a pending data packet count for one or more data packets associated with data to be forwarded from a node to another node on a communication link and then comparing the pending data packet count to a threshold data packet count value. The method further includes forwarding the one or more data packets to the other node at a rate based on the comparison.

Abstract: Method and apparatus to perform cyclic redundancy check computations for error detection are described.

Abstract: In a method of allocating a shared resource among a plurality of competing applicants, a share of the resource allocated to one of the applicants is limited on the basis of a current proportion of the resource allocated to the applicant and a total of respective shares of the resource currently allocated to all of the applicants.

Abstract: A method, apparatus, and system for limiting latency.

Abstract: An ATM switch having a plurality of input-ports and a plurality of output ports allowing a plurality of priority levels, which is highly modular allowing expansion of the number of cell buffers in a shared buffer pool, thus efficiently handling bursty traffic of one-to-one and one-to-many destination ports, using the bit slicing concept to reduce the operating speed of the switch, and decrease the cell buffer size requirement per slice along with reducing the number of shared queue memories per slice, aiding cost effective and efficient, very large scale integration (VLSI) implementation. It also allows configurability of input link speeds, taking care of the order of cell delivery to the output ports. The switch on receiving the input cell, searches for a free buffer in the shared pool, then routes the cell into this buffer and indexes the pointer into an output queue called the queue management module which uses a shared pool of queue memories.