Abstract: A circuit tests a memory having a cell array accessible through first and second ports, the circuit comprising an address generation circuit for generating an internal address consisting of a row selection address and a column selection address in response to an external address consisting of a row selection address and a column selection address, wherein an adder generates the internal row selection address for addressing a second row of the cell array through the second port by incrementing the external row selection address for addressing a first row of the cell array through the first port, such that the first row and the second row form adjacent rows within the cell array, and a data generation circuit for generating internal test data responsive to external test data, wherein the external test data for the first port is inverted when the cell array is accessed through the second port.

Abstract: Embedded testing circuit for testing a dual port memory having a memory cell array being accessible through a first port (A) and a second port (B), said embedded testing circuit comprising an embedded address generation circuit for generating an internal address consisting of an internal row selection address (RSAint) and an internal column selection address (CSAint) in response to an external address consisting of an external row selection address (RSAext) and an external column selection address (CSAext), wherein said internal row selection address (RSAint) for addressing a second row of said memory cell array through said second port (B) is generated by an adder which increments the external row selection address (RSAext) for addressing a first row of said memory cell array through said first port (A), such that the first row and said second row form adjacent rows within said memory cell array, wherein said internal column selection address (CSAint) for addressing a column of said memory cell array through