Patents by Inventor Jainaveen Sundaram Priya

Jainaveen Sundaram Priya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230198468
    Abstract: Various embodiments provide apparatuses, systems, and methods for resonant rotary clocking to generate synchronized clock signals. A base die may include a resonant ring structure to form a plurality of rotary traveling wave oscillators (RTWOs) coupled to one another in a rotary oscillator array (ROA). The ROA may provide synchronized clock signals at deterministic phase points that are tapped from the resonant ring structure. Multiple dies may be coupled to the base die (e.g., in a multi-die system) and may receive the tapped clock signals. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Vinayak Honkote, Ragh Kuttappa, Satish Yada, Tanay Karnik, Dileep J. Kurian, Jainaveen Sundaram Priya
  • Publication number: 20230077750
    Abstract: Embodiments disclosed herein include die modules. In an embodiment, a die module comprises a plurality of first dies, and a second die under the plurality of first dies. In an embodiment, the second die is coupled to individual ones of the plurality of first dies. In an embodiment, the second die comprises a plurality of mesh stops, and conductive routing to electrically couple the mesh stops together.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Tanay KARNIK, Dileep KURIAN, Bradley JACKSON, Srivatsa RANGACHAR SRINIVASA, Jainaveen SUNDARAM PRIYA, Adel A. ELSHERBINI
  • Publication number: 20220319162
    Abstract: Methods, apparatus, systems, and articles of manufacture providing a Bayesian compute unit with reconfigurable sampler and methods and apparatus to operate the same are disclosed. An example apparatus includes a number generator to generate a sequence of numbers; a multiplier to generate a plurality of products by multiplying respective numbers of the sequence of the numbers by a variance value; and an adder to generate a plurality of weights by adding a mean value to the plurality of products, the plurality of weights corresponding to a single probability distribution.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Srivatsa Rangachar Srinivasa, Tanay Karnik, Dileep Kurian, Ranganath Krishnan, Jainaveen Sundaram Priya, Indranil Chakraborty
  • Publication number: 20220101091
    Abstract: A DNN accelerator includes a multiplication controller controlling whether to perform matrix computation based on weight values. The multiplication controller reads a weight matrix from a WRAM in the DNN accelerator and determines a row value for a row in the weight matrix. In an embodiment where the row value is one, a first switch sends a read request to the WRAM to read weights in the row and a second switch forms a data transmission path from an IRAM in the DNN accelerator to a PE in the DNN accelerator. The PE receives the weights and input data stored in the IRAM and performs MAC operations. In an embodiment where the row value is zero, the first and second switches are not triggered. No read request is sent to the WRAM and the data transmission path is not formed. The PE will not perform any MAC operations.
    Type: Application
    Filed: December 14, 2021
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Srivatsa Rangachar Srinivasa, Jainaveen Sundaram Priya, Bradley A. Jackson, Ambili Vengallur, Dileep John Kurian, Tanay Karnik
  • Publication number: 20220012570
    Abstract: Methods, apparatus, systems, and articles of manufacture providing a Bayesian compute unit with reconfigurable sampler and methods and apparatus to operate the same are disclosed. An example apparatus includes a processor element to generate (a) a first element by applying a mean value to an activation and (b) a second element by applying a variance value to a square of the activation, the mean value and the variance value corresponding to a single probability distribution; a programmable sampling unit to: generate a pseudo random number; and generate an output based on the pseudo random number, the first element, and the second element, wherein the output corresponds to the single probability distribution; and output memory to store the output.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Srivatsa Rs, Indranil Chakraborty, Ranganath Krishnan, Uday A Korat, Muluken Hailesellasie, Jainaveen Sundaram Priya, Deepak Dasalukunte, Dileep Kurian, Tanay Karnik
  • Publication number: 20210385463
    Abstract: In one embodiment, a compute device includes interface circuitry and processing circuitry. The processing circuitry receives, via the interface circuitry, a current frame of a video stream to be encoded. The processing circuitry then determines whether a scene change occurs at the current frame. If a scene change occurs at the current frame, the processing circuitry detects the scene in the current frame by performing pixel segmentation on the current frame. If a scene change does not occur at the current frame, the processing circuitry detects the scene in the current frame by performing motion estimation on the current frame relative to a previous frame in which the scene was detected. Based on the scene detected in the current frame, the processing circuitry then generates one or more encoding parameters and provides those parameters to a video encoder to encode the current frame.
    Type: Application
    Filed: August 20, 2021
    Publication date: December 9, 2021
    Applicant: Intel Corporation
    Inventors: Palanivel Guruva reddiar, Praveen P. Nair, Shabbir Abbasali Saifee, Vikas Ahuja, Arshad Mehmood, Jainaveen Sundaram Priya