Patents by Inventor Jair do Nascimento

Jair do Nascimento has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8116053
    Abstract: An isolating device for a power semiconductor comprising n power terminals for a power grid comprises n module terminals, n grid terminals, n connecting lines which connect the module terminals and grid terminals and have overcurrent fuses, and a tripping controller. The tripping controller includes a detector for detecting the rupture of an overcurrent fuse and a tripping unit for tripping an overcurrent fuse. A power module contains a power semiconductor and an isolating device. A system installation contains at least two power modules connected in parallel. In a method for operating an isolating device, at least one of the overcurrent fuses is tripped upon a predetermined tripping criterion being met.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: February 14, 2012
    Assignee: Semikron Elektronik GmbH & Co. KG
    Inventors: Jair Do Nascimento, Roland Bittner
  • Publication number: 20090225485
    Abstract: An isolating device for a power semiconductor comprising n power terminals for a power grid comprises n module terminals, n grid terminals, n connecting lines which connect the module terminals and grid terminals and have overcurrent fuses, and a tripping controller. The tripping controller includes a detector for detecting the rupture of an overcurrent fuse and a tripping unit for tripping an overcurrent fuse. A power module contains a power semiconductor and an isolating device. A system installation contains at least two power modules connected in parallel. In a method for operating an isolating device, at least one of the overcurrent fuses is tripped upon a predetermined tripping criterion being met.
    Type: Application
    Filed: March 2, 2009
    Publication date: September 10, 2009
    Applicant: SEMIKRON Elektronik GmbH & Co.KG
    Inventors: Jair Do NASCIMENTO, Roland Bittner
  • Patent number: 7038500
    Abstract: A current regulated circuit arrangement for controlling a power semiconductor transistor, as example a MOSFET or IGBT power transistor, that includes at least two mirror-symmetrically arranged regulated power sources and an output voltage regulator. A first regulated power source is fed from an unregulated power source and controls the gate of the power transistor such that the power transistor is switched into the conductive state. A second regulated power source is fed from an unregulated power source and controls the gate of the power transistor such that the power transistor is switched into the non-conductive state. A voltage regulator or limiter limits the current at the gate of the power transistor to a operably suitable maximum value.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: May 2, 2006
    Assignee: Semikron Elektronik GmbH & Co. KG
    Inventor: Jair do Nascimento