Abstract: An equalizer circuit includes: a main stage circuit including: a main stage differential pair; and a main stage degeneration resistance; a replica stage circuit including: a replica stage differential pair matching the main stage differential pair; and a replica stage degeneration resistance matching the main stage degeneration resistance and disconnected from the replica stage differential pair; equalizer inputs connected to: gate electrodes of the main stage differential pair; and gate electrodes of the replica stage differential pair; and equalizer outputs connected to: a main stage positive output and a main stage negative output connected to drain electrodes of the main stage differential pair; and a replica stage positive output and a replica stage negative output connected to drain electrodes of the replica stage differential pair, the replica stage positive output connected to the main stage negative output and the replica stage negative output connected to the main stage positive output.

Abstract: An inductor structure includes a first inductor and a second inductor. A first portion of the first inductor is disposed on a first layer and a second portion of the first inductor is disposed on a second layer. A first portion of the second inductor is disposed on the first layer and a second portion of the second inductor is disposed on the second layer. The first portion of the first inductor and the second portion of the second inductor at least partially overlap. The second portion of the first inductor and the first portion of the second inductor at least partially overlap.

Abstract: A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.

Abstract: A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.