Patents by Inventor Jairus L. Pisigan
Jairus L. Pisigan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9721925Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.Type: GrantFiled: October 14, 2014Date of Patent: August 1, 2017Assignee: STATS ChipPAC, Pte. Ltd.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Patent number: 9472427Abstract: A semiconductor device has a leadframe with first and second opposing surfaces and a plurality of notched fingers. The leadframe is mounted to a carrier. A first semiconductor die is mounted over the carrier between the notched fingers. Conductive TSVs are formed through the first semiconductor die. A bond wire is formed between a first contact pad on the first semiconductor die and notched finger. The conductive TSV are electrically connected to the bond wires. An encapsulant is deposited over the first semiconductor die and notched fingers. Bumps are formed over the first surface of the leadframe. The carrier is removed and the leadframe is singulated. The leadframe and first semiconductor die is mounted to a substrate. A second semiconductor die is mounted to a second contact pad on the first semiconductor die. A third semiconductor die is mounted to the second surface of the leadframe.Type: GrantFiled: March 22, 2011Date of Patent: October 18, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Publication number: 20150028496Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.Type: ApplicationFiled: October 14, 2014Publication date: January 29, 2015Applicant: STATS CHIPPAC, LTD.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Patent number: 8890328Abstract: A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.Type: GrantFiled: December 6, 2011Date of Patent: November 18, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Jairus L. Pisigan, Frederick R. Dahilig
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Patent number: 8872320Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.Type: GrantFiled: January 23, 2012Date of Patent: October 28, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Patent number: 8802505Abstract: A semiconductor device is made by forming solder bumps on a first side of a semiconductor wafer. A protective layer is formed on a second side of the semiconductor wafer opposite the first side. The protective layer can be adhesive paste, laminated film, spin-coated resin, epoxy based elastomer, organic rubbery material, polystyrene, polyethylene terephthalate, or other polymer material. The semiconductor wafer is singulated into semiconductor die. The semiconductor die is mounted to a carrier. A molding compound is formed around the semiconductor die. The protective layer provides stress relief for the semiconductor die. The protective layer is removed from the semiconductor die. The protective layer can provide a thermal dissipation, in which case it is made with metal or polymer-based material with a filler such as alumina, zinc oxide, silicon dioxide, silver, aluminum, and aluminum nitride.Type: GrantFiled: September 30, 2008Date of Patent: August 12, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Publication number: 20120241915Abstract: A semiconductor device has a leadframe with first and second opposing surfaces and a plurality of notched fingers. The leadframe is mounted to a carrier. A first semiconductor die is mounted over the carrier between the notched fingers. Conductive TSVs are formed through the first semiconductor die. A bond wire is formed between a first contact pad on the first semiconductor die and notched finger. The conductive TSV are electrically connected to the bond wires. An encapsulant is deposited over the first semiconductor die and notched fingers. Bumps are formed over the first surface of the leadframe. The carrier is removed and the leadframe is singulated. The leadframe and first semiconductor die is mounted to a substrate. A second semiconductor die is mounted to a second contact pad on the first semiconductor die. A third semiconductor die is mounted to the second surface of the leadframe.Type: ApplicationFiled: March 22, 2011Publication date: September 27, 2012Applicant: STATS CHIPPAC, LTD.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Publication number: 20120119361Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Applicant: STATS CHIPPAC, LTD.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Publication number: 20120074567Abstract: A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.Type: ApplicationFiled: December 6, 2011Publication date: March 29, 2012Applicant: STATS ChipPAC, Ltd.Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Jairus L. Pisigan, Frederick R. Dahilig
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Patent number: 8110440Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.Type: GrantFiled: May 18, 2009Date of Patent: February 7, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Patent number: 8105915Abstract: A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.Type: GrantFiled: June 12, 2009Date of Patent: January 31, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Jairus L. Pisigan, Frederick R. Dahilig
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Publication number: 20100314780Abstract: A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Jairus L. Pisigan, Frederick R. Dahilig
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Publication number: 20100289131Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.Type: ApplicationFiled: May 18, 2009Publication date: November 18, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
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Publication number: 20100078834Abstract: A semiconductor device is made by forming solder bumps on a first side of a semiconductor wafer. A protective layer is formed on a second side of the semiconductor wafer opposite the first side. The protective layer can be adhesive paste, laminated film, spin-coated resin, epoxy based elastomer, organic rubbery material, polystyrene, polyethylene terephthalate, or other polymer material. The semiconductor wafer is singulated into semiconductor die. The semiconductor die is mounted to a carrier. A molding compound is formed around the semiconductor die. The protective layer provides stress relief for the semiconductor die. The protective layer is removed from the semiconductor die. The protective layer can provide a thermal dissipation, in which case it is made with metal or polymer-based material with a filler such as alumina, zinc oxide, silicon dioxide, silver, aluminum, and aluminum nitride.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan