Patents by Inventor Jais Abraham
Jais Abraham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935606Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.Type: GrantFiled: June 30, 2021Date of Patent: March 19, 2024Assignee: QUALCOMM IncorporatedInventors: Rahul Sahu, Sharad Kumar Gupta, Jung Pill Kim, Chulmin Jung, Jais Abraham
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Publication number: 20230005556Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Rahul SAHU, Sharad Kumar GUPTA, Jung Pill KIM, Chulmin JUNG, Jais ABRAHAM
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Patent number: 10996267Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.Type: GrantFiled: January 23, 2019Date of Patent: May 4, 2021Assignee: QUALCOMM INCORPORATEDInventors: Jais Abraham, Punit Kishore
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Publication number: 20200233031Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Inventors: Jais ABRAHAM, Punit KISHORE
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Patent number: 10656203Abstract: Certain aspects of the present disclosure provide an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.Type: GrantFiled: February 18, 2019Date of Patent: May 19, 2020Assignee: QUALCOMM IncorporatedInventors: Punit Kishore, Jais Abraham, Pawan Chhabra
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Patent number: 7421634Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).Type: GrantFiled: June 15, 2005Date of Patent: September 2, 2008Assignee: Texas Instruments IncorporatedInventors: Naga Satya Srikanth Puvvada, Nikila Krishnamoorthy, Sandeep Jain, Jais Abraham
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Patent number: 7404126Abstract: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.Type: GrantFiled: March 29, 2006Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Sandeep Jain, Jais Abraham
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Patent number: 7352169Abstract: Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.Type: GrantFiled: May 26, 2006Date of Patent: April 1, 2008Assignee: Texas Instruments IncorporatedInventors: Jais Abraham, Rohit Goel
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Publication number: 20080001616Abstract: Testing the components of I/O paths in an integrated circuit at at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.Type: ApplicationFiled: May 26, 2006Publication date: January 3, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jais ABRAHAM, Rohit GOEL
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Publication number: 20070234150Abstract: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.Type: ApplicationFiled: March 29, 2006Publication date: October 4, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sandeep Jain, Jais Abraham
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Publication number: 20060248422Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).Type: ApplicationFiled: June 15, 2005Publication date: November 2, 2006Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Naga Satya Puvvada, Nikila Krishnamoorthy, Sandeep Jain, Jais Abraham
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Patent number: 7082558Abstract: A non-robust test pattern, which causes a transition on a path of interest as well as off-paths, may be selected as being suitable for performing delay analysis of the path of interest (e.g., critical path) if the transitions caused on the off-paths would not overlap with the transition caused on the path of interest. In other words, an aspect of the present invention enables at least some non-robust test patterns to be used for performing delay analysis. As non-robust test patterns (as well as robust test patterns) can be used to perform delay analysis, the number of possible test patterns for performing speed analysis can be increased.Type: GrantFiled: November 25, 2002Date of Patent: July 25, 2006Assignee: Texas Instruments IncorporatedInventors: Ajit D. Gupte, Shankaranarayana Karantha Deshamangala, Amit Brahme, Jais Abraham
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Patent number: 6981190Abstract: A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch multiplexor may be employed in addition to a scan multiplexor, which enables the test pattern bits or normal operating input to be selected and stored in the desired memory element. The scan multiplexor is used to scan-in a test pattern and evaluate a first input, and the launch multiplexor provides the control to store a desired bit into the corresponding memory element. Another output may be evaluated after storing the desired bit. In an embodiment, launch multiplexors are used associated with only memory elements in the critical paths, and the delay in transitioning from one output to another may be conveniently measured.Type: GrantFiled: September 30, 2002Date of Patent: December 27, 2005Assignee: Texas Instruments IncorporatedInventors: Ajit D. Gupte, Jais Abraham
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Patent number: 6853212Abstract: A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer is gated by a scan enable input so that the scan output is quiescent when the storage circuit is not in scan mode. The selectively enabled scan output buffer is embodied with only four transistors.Type: GrantFiled: December 20, 2002Date of Patent: February 8, 2005Assignee: Texas Instruments IncorporatedInventors: G. Subash Chandar, Jais Abraham
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Publication number: 20040119502Abstract: A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer is gated by a scan enable input so that the scan output is quiescent when the storage circuit is not in scan mode. The selectively enabled scan output buffer is embodied with only four transistors.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: G. Subash Chandar, Jais Abraham
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Publication number: 20040103352Abstract: A non-robust test pattern, which causes a transition on a path of interest as well as off-paths, may be selected as being suitable for performing delay analysis of the path of interest (e.g., critical path) if the transitions caused on the off-paths would not overlap with the transition caused on the path of interest. In other words, an aspect of the present invention enables at least some non-robust test patterns to be used for performing delay analysis. As non-robust test patterns (as well as robust test patterns) can be used to perform delay analysis, the number of possible test patterns for performing speed analysis can be increased.Type: ApplicationFiled: November 25, 2002Publication date: May 27, 2004Applicant: Texas Instruments IncorporatedInventors: Ajit D. Gupte, Shankaranarayana Karantha Deshamangala, Amit Brahme, Jais Abraham
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Publication number: 20040064769Abstract: A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch multiplexor may be employed in addition to a scan multiplexor, which enables the test pattern bits or normal operating input to be selected and stored in the desired memory element. The scan multiplexor is used to scan-in a test pattern and evaluate a first input, and the launch multiplexor provides the control to store a desired bit into the corresponding memory element. Another output may be evaluated after storing the desired bit. In an embodiment, launch multiplexors are used associated with only memory elements in the critical paths, and the delay in transitioning from one output to another may be conveniently measured.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Applicant: Texas Instruments IncorporatedInventors: Ajit D. Gupte, Jais Abraham