Patents by Inventor Jaison Daniel Kurien

Jaison Daniel Kurien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performing testing utilizing staggered clocks
    Patent number: 11668750
    Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: June 6, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane, Shantanu Sarangi, Purnabha Majumder
  • PERFORMING TESTING UTILIZING STAGGERED CLOCKS
    Publication number: 20230089800
    Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 23, 2023
    Inventors: Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane, Shantanu Sarangi, Purnabha Majumder