Patents by Inventor Jaiswal Akhilesh

Jaiswal Akhilesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for differential bit operation and methods for fabricating the same
    Patent number: 10468456
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Integrated circuits including magnetic random access memory structures and methods for fabricating the same
    Patent number: 10411069
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: September 10, 2019
    Assignee: Globalfoundries, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES HAVING REDUCED SWITCHING ENERGY BARRIERS FOR DUAL BIT OPERATION AND METHODS FOR FABRICATING THE SAME
    Publication number: 20190259809
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 22, 2019
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES HAVING REDUCED SWITCHING ENERGY BARRIERS FOR DIFFERENTIAL BIT OPERATION AND METHODS FOR FABRICATING THE SAME
    Publication number: 20190259810
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 22, 2019
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES AND METHODS FOR FABRICATING THE SAME
    Publication number: 20190259808
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 22, 2019
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for dual bit operation and methods for fabricating the same
    Patent number: 10381406
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: August 13, 2019
    Assignee: Globalfoundries, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh