Abstract: The present disclosure may provide a device and method for independent phase adjustment of a PAM receiver. The device includes: a plurality of samplers configured to perform sampling for signal level decision of multi-level input data; a global clock source configured to provide a common sampling clock to the samplers; and a plurality of phase adjusters configured to respectively adjust a phase of the common sampling clock to provide a sampling phase applied to a corresponding sampler. According to the present disclosure, it is possible to achieve reliable BER performance by independently adjusting a sampling phase of a sampler corresponding to each eye opening even in the presence of unsymmetric eye openings.

Abstract: The present disclosure may provide a device and method for independent phase adjustment of a PAM receiver. The device includes: a plurality of samplers configured to perform sampling for signal level decision of multi-level input data; a global clock source configured to provide a common sampling clock to the samplers; and a plurality of phase adjusters configured to respectively adjust a phase of the common sampling clock to provide a sampling phase applied to a corresponding sampler. According to the present disclosure, it is possible to achieve reliable BER performance by independently adjusting a sampling phase of a sampler corresponding to each eye opening even in the presence of unsymmetric eye openings.

Abstract: A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively. The group select circuit, in response to receiving a control signal through the at least one control line, is configured to transmit chip enable signals to a selected memory group among the first nonvolatile memory group and the second nonvolatile memory group through selected chip enable lines among the first chip enable lines and the second chip enable lines.

Abstract: A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively. The group select circuit, in response to receiving a control signal through the at least one control line, is configured to transmit chip enable signals to a selected memory group among the first nonvolatile memory group and the second nonvolatile memory group through selected chip enable lines among the first chip enable lines and the second chip enable lines.