Patents by Inventor Jake Truelove
Jake Truelove has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11734188Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.Type: GrantFiled: March 11, 2021Date of Patent: August 22, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles D. Wait, David Campbell, Jake Truelove, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Patent number: 11636043Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.Type: GrantFiled: August 30, 2021Date of Patent: April 25, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles D. Wait, Jake Truelove, David Campbell, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Publication number: 20230062909Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Charles D. Wait, Jake Truelove, David Campbell, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Patent number: 11556475Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.Type: GrantFiled: March 29, 2021Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait, Jody Joyner
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Publication number: 20220309000Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to initiate a first prefetch request based on the demand access stream and perform a first prefetch that includes performing a translation lookaside buffer (TLB) lookup on a TLB structure in response to the first prefetch request. The processor determines a TLB entry in response to performing the TLB lookup and performs at least one second prefetch based on the TLB entry without performing a subsequent TLB lookup on the TLB structure.Type: ApplicationFiled: March 29, 2021Publication date: September 29, 2022Inventors: David Campbell, George W. Rohrbaugh, III, Jake Truelove, Jon K. Kriegel, Charles D. Wait, Jody Joyner
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Publication number: 20220292028Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: Charles D. Wait, David Campbell, Jake Truelove, Jody Joyner, Jon K. Kriegel, Glenn O. Kincaid
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Patent number: 11422947Abstract: A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.Type: GrantFiled: August 12, 2020Date of Patent: August 23, 2022Assignee: International Business Machines CorporationInventors: David Campbell, Jake Truelove, Charles D. Wait, Jon K. Kriegel
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Publication number: 20220050792Abstract: A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.Type: ApplicationFiled: August 12, 2020Publication date: February 17, 2022Inventors: David Campbell, Jake Truelove, Charles D. Wait, Jon K. Kriegel
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Patent number: 11210233Abstract: A method and system of managing addresses translations where in response to a request to invalidate an address translation, the scope of the address translation invalidation operation is determined; an address translation invalidation probe is installed or activated in a memory management unit (MMU) pipeline; whether an address translation undergoing a table walk operation is within a scope of the address translation invalidation probe is determined; and in response to the address translation undergoing a table walk operation being within the scope of the address translation invalidation probe, preventing or blocking the table walk operation from writing data to a translation buffer in the MMU. The probe also performs an address translation comparison to determine whether an address translation request coming down the MMU pipeline is within the scope of the probe, and if within the scope of the probe, prevents, blocks and/or rejects the address translation.Type: GrantFiled: January 7, 2020Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Jake Truelove, David Campbell
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Patent number: 11119945Abstract: A system of handling electronic information having a virtually tagged cache having a directory and a plurality of entries containing data, the directory containing multiple entries, each entry configured to comprise at least a virtual address and one of a plurality of context tags, wherein each context tag is an encoding for one of a plurality of layers of address space; a context tag table having a plurality of entries, each entry configured to map one of the plurality of context tags to one of the plurality of layers of space; and a scratch register containing a current context tag for a current layer of address space on which the processor is operating. The virtually tagged cache is configured to preserve information in the virtually tagged cache when performing a context switch in the system.Type: GrantFiled: April 23, 2020Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventors: Jake Truelove, David Campbell, Bryan Lloyd
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Publication number: 20210209031Abstract: A method and system of managing addresses translations where in response to a request to invalidate an address translation, the scope of the address translation invalidation operation is determined; an address translation invalidation probe is installed or activated in a memory management unit (MMU) pipeline; whether an address translation undergoing a table walk operation is within a scope of the address translation invalidation probe is determined; and in response to the address translation undergoing a table walk operation being within the scope of the address translation invalidation probe, preventing or blocking the table walk operation from writing data to a translation buffer in the MMU. The probe also performs an address translation comparison to determine whether an address translation request coming down the MMU pipeline is within the scope of the probe, and if within the scope of the probe, prevents, blocks and/or rejects the address translation.Type: ApplicationFiled: January 7, 2020Publication date: July 8, 2021Inventors: Jake Truelove, David Campbell
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Patent number: 10776281Abstract: An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.Type: GrantFiled: October 4, 2018Date of Patent: September 15, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jake Truelove, Ronald Kalla, Jody Joyner, Benjamin Herrenschmidt, David A. Larson Stanton
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Publication number: 20200110710Abstract: An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Jake Truelove, Ronald Kalla, Jody Joyner, Benjamin HERRENSCHMIDT, David A. Larson Stanton