Abstract: A graphics processor operable to render frames that represent a view of a scene using a ray tracing process includes a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process. The ray tracing circuit comprises a ray testing circuit operable to perform ray intersection tests for nodes of a ray tracing acceleration data structure and storage local to the ray testing circuit for storing data representative of one or more nodes of a ray tracing acceleration data structure for use by the ray testing circuit. Rays for testing by the ray testing circuit are selected from a pool of one or more rays to be tested based on an indication of the ray tracing acceleration data structure node or nodes that have been stored in the local storage of the ray testing circuit.

Abstract: A graphics processor that is operable to perform ray tracing is disclosed. When it is determined that a ray tracing circuit of the graphics processor may require additional storage space to store test record entries to trace a ray, additional storage space is allocated for the ray tracing circuit to use to store test record entries to trace the ray.

Abstract: A method of operating a graphics processor to perform ray tracing. The graphics processor includes a ray tracing circuit that can be messaged by the graphics processor's programmable execution unit during execution of a program to perform a respective traversal of the at least one ray tracing acceleration data structure to be traversed for that ray. The ray tracing circuit when returning rays' processing to the programmable execution unit is operable to group rays together for continued execution by the programmable execution unit as a respective thread group.

Abstract: A method of operating a graphics processor to perform ray tracing. The graphics processor includes a ray tracing circuit that can be messaged by the graphics processor's programmable execution unit during execution of a program to perform a respective traversal of the at least one ray tracing acceleration data structure to be traversed for that ray. The ray tracing circuit may need to stop a ray's traversal to return the ray's processing to the programmable execution unit before the ray's traversal is subsequently restarted. In that case, the ray's traversal is restarted from the beginning.

Abstract: A graphics processor that is operable to perform ray tracing is disclosed. When it is determined that a ray intersects a volume represented by a node of a ray tracing acceleration data structure that is associated with a bounding volume primitive, the ray is not tested against the bounding volume primitive to determine whether the ray intersects the bounding volume primitive.

Abstract: A graphics processor performs graphics processing in respect of a region of a render output. The graphics processing comprises obtaining a scaling factor corresponding to a desired resolution for the region. The graphics processing further comprises, in accordance with the desired resolution, obtaining scaled graphics geometry to be rendered for the region and selecting a subregion of the region to be rendered in respect of the region. The selected subregion is then rendered using the scaled graphics geometry, thereby providing a subregion of data elements rendered in accordance with the desired resolution. The graphics processor can provide efficient and flexible graphics processing when performing variable resolution rendering.

Abstract: There is disclosed a method of storing an encoded block of data in memory comprising encoding a block of data elements and determining a memory location (26) at which the encoded block of data is to be stored. The memory location (26) at which the encoded block of data is stored is then indicated in a header (406) for the encoded block of data by including in the header a memory address value (407) together with a modifier value (500) representing a modifier that is to be applied to the memory address value (407) when determining the memory location (26). When the encoded block of data is to be retrieved, the header (406) is read and processed to determine the memory location (26).

Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

Abstract: A data processing system comprises encoding circuitry operable to encode arrays of data elements, decoding circuitry operable to decode encoded versions of arrays of data elements, and consumer circuitry operable to use arrays of data elements. Data indicative of a resolution that is to be used by the consumer circuitry for at least one region of the array of data elements is provided to the encoding circuitry, and the encoding circuitry uses the data indicative of the resolution that is to be used by the consumer circuitry to control the generation of the representation for representing at least one block that the array of data elements is divided into.

Abstract: When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.

Abstract: There is disclosed a method of storing an encoded block of data in memory comprising encoding a block of data elements and determining a memory location (26) at which the encoded block of data is to be stored. The memory location (26) at which the encoded block of data is stored is then indicated in a header (406) for the encoded block of data by including in the header a memory address value (407) together with a modifier value (500) representing a modifier that is to be applied to the memory address value (407) when determining the memory location (26). When the encoded block of data is to be retrieved, the header (406) is read and processed to determine the memory location (26).

Abstract: Disclosed herein is a method and apparatus for determining decoded data values for a data element of an array of data elements from an encoded representation of the array of data elements, wherein the decoding comprises determining which, if any, bits are missing for the data value(s) for the data element and selecting based on this an adjustment scheme to be applied for the data value(s) for the data element from a plurality of available adjustment schemes. Also disclosed are a method and apparatus for generating an encoding hint comprising an indication of the one or more encoding parameters that were used to generate the encoded representation which encoding hint can then be associated with the decoded data and then used when the decoded data is subsequently to be encoded.

Abstract: A data processing system includes a producer processor that produces a sequence of data outputs for use by consumer processors of the data processing system. The system also includes a memory for storing a sequence of data outputs produced by the data processor. The data processor encodes data outputs as encoded blocks of data, storing a particular encoded block of a first frame in a first location in the memory and an indication of the first location. The data processor stores a corresponding encoded block of a second data output in a second location and updates the indication to the second location.

Abstract: Disclosed herein is a method and apparatus for determining decoded data values for a data element of an array of data elements from an encoded representation of the array of data elements, wherein the decoding comprises determining which, if any, bits are missing for the data value(s) for the data element and selecting based on this an adjustment scheme to be applied for the data value(s) for the data element from a plurality of available adjustment schemes. Also disclosed are a method and apparatus for generating an encoding hint comprising an indication of the one or more encoding parameters that were used to generate the encoded representation which encoding hint can then be associated with the decoded data and then used when the decoded data is subsequently to be encoded.

Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

Abstract: A graphics processor includes a rasteriser, an early depth tester, a renderer, a late depth tester, and a depth test data buffer that stores depth data values for use by the early and late depth testers. When a fragment is to undergo an early depth test to update the depth buffer, it is first determined whether the fragment should undergo the early depth test to update the depth buffer without waiting for any other fragment to undergo a depth test, or whether the result of a late depth test on a fragment that is still to undergo a late depth test should be awaited before performing a depth test to update the depth buffer on the fragment.

Abstract: When storing an array of data in memory, the data array is divided into a plurality of blocks, and for respective groups of the blocks that the data array has been divided into, a set of data representing the group of blocks that includes: for each block of the group of blocks, a set of data for that block of the group of blocks; and a size indication for each of one or more of the blocks of the group of blocks, the size indication for a block of a group of blocks indicating the size in memory of the set of data for that block of the group included in the stored set of data representing the group of blocks, is stored. A set of header data is also stored separately for each group of blocks of the data array.

Abstract: When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.