Patents by Inventor Jakob Kriz
Jakob Kriz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11276624Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.Type: GrantFiled: December 17, 2019Date of Patent: March 15, 2022Assignee: Infineon Technologies Austria AGInventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
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Publication number: 20210183732Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
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Patent number: 9064875Abstract: Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layer.Type: GrantFiled: November 21, 2011Date of Patent: June 23, 2015Assignee: Infineon Technologies AGInventors: Jakob Kriz, Norbert Urbansky
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Integrated circuit arrangement including vias having two sections, and method for producing the same
Patent number: 8273658Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.Type: GrantFiled: August 25, 2005Date of Patent: September 25, 2012Assignee: Infineon Technologies AGInventors: Klaus Goller, Jakob Kriz -
Publication number: 20120112350Abstract: Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layerType: ApplicationFiled: November 21, 2011Publication date: May 10, 2012Inventors: Jakob Kriz, Norbert Urbansky
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Patent number: 8008161Abstract: A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.Type: GrantFiled: June 20, 2005Date of Patent: August 30, 2011Assignee: Infineon Technologies AGInventors: Jens Bachmann, Bernd Föste, Klaus Goller, Jakob Kriz
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Patent number: 7557444Abstract: A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.Type: GrantFiled: September 20, 2006Date of Patent: July 7, 2009Assignee: Infineon Technologies AGInventors: Achim Gratz, Jakob Kriz, Woong-Jae Chung
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Publication number: 20080303169Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.Type: ApplicationFiled: August 25, 2005Publication date: December 11, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Klaus Goller, Jakob Kriz
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Publication number: 20080067688Abstract: A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.Type: ApplicationFiled: September 20, 2006Publication date: March 20, 2008Inventors: Achim Gratz, Jakob Kriz, Woong-Jae Chung
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Publication number: 20070194301Abstract: One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.Type: ApplicationFiled: November 24, 2004Publication date: August 23, 2007Inventors: Recai Sezi, Andreas Walter, Reimund Engl, Anna Maltenberger, Christine Dehm, Sitaram Arkalgud, Igor Kasko, Joachim Nuetzel, Jakob Kriz, Thomas Mikolajick, Cay-Uwe Pinnow
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Patent number: 7060583Abstract: In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an insulating material will now be applied, wherein the at least one layer is patterned such that at least one section of the basis region is exposed. Next, a layer of a polycrystalline semiconductor material of the first conductivity type, which is heavily doped with doping atoms, will be generated such that the exposed section is essentially covered. Now, a second layer of a highly conductive material on the layer of the polycrystalline semiconductor material will be generated in order to form an emitter double layer with the same.Type: GrantFiled: January 13, 2004Date of Patent: June 13, 2006Assignee: Infineon Technologies AGInventors: Jakob Kriz, Martin Seck, Armin Tilke
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Publication number: 20050287755Abstract: A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.Type: ApplicationFiled: June 20, 2005Publication date: December 29, 2005Inventors: Jens Bachmann, Bernd Foste, Klaus Goller, Jakob Kriz
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Patent number: 6844584Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.Type: GrantFiled: August 9, 2001Date of Patent: January 18, 2005Assignee: Infineon Technologies AGInventors: Herbert Palm, Josef Willer, Achim Gratz, Jakob Kriz, Mayk Roehrich
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Publication number: 20040185631Abstract: In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an insulating material will now be applied, wherein the at least one layer is patterned such that at least one section of the basis region is exposed. Next, a layer of a polycrystalline semiconductor material of the first conductivity type, which is heavily doped with doping atoms, will be generated such that the exposed section is essentially covered. Now, a second layer of a highly conductive material on the layer of the polycrystalline semiconductor material will be generated in order to form an emitter double layer with the same.Type: ApplicationFiled: January 13, 2004Publication date: September 23, 2004Applicant: Infineon Technologies AGInventors: Jakob Kriz, Martin Seck, Armin Tilke
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Patent number: 6654281Abstract: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.Type: GrantFiled: June 20, 2002Date of Patent: November 25, 2003Assignee: Infineon Technologies AGInventors: Georg Georgakos, Kai Huckels, Jakob Kriz, Christoph Kutter, Andreas Liebelt, Christoph Ludwig, Elard Stein von Kamienski, Peter Wawer
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Publication number: 20030015752Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.Type: ApplicationFiled: August 9, 2001Publication date: January 23, 2003Applicant: Infineon Technologies AGInventors: Herbert Palm, Josef Willer, Achim Gratz, Jakob Kriz, Mayk Roehrich
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Publication number: 20030007386Abstract: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.Type: ApplicationFiled: June 20, 2002Publication date: January 9, 2003Inventors: Georg Georgakos, Kai Huckels, Jakob Kriz, Christoph Kutter, Andreas Liebelt, Christoph Ludwig, Elard Stein Von Kamienski, Peter Wawer