Abstract: A C-MOS oscillator circuit having input and output terminals adapted to be connected to a resonator and two active MOS transistors of complementary types connected in series between the supply terminals of the circuit, which supply terminals are connected to the positive and negative poles of a source of d.c. voltage, the sources of the transistors being connected to a supply terminal and the drains being connected to the output terminal. The d.c. bias and the a.c. voltage control of each of the active transistors are ensured by a MOS transistor of the same type connected as a diode between its gate and its drain, a current source connected between its gate and the supply terminal to which the source of the other active transistor is connected, and a capacitive voltage divider which is connected between the supply terminal, to which its source is connected, and the input terminal, and the intermediate point of which is connected to its gate.

Abstract: To regulate the threshold voltage of insulated-gate field-effect transistors (IGFETs) in an integrated circuit, such as that of an electronic wristwatch, capacitors and other IGFETs of the same conductivity type as those of the controlled circuit are incorporated in the substrate thereof to form a regulating transistor, a constant-current generator and one or more voltage multipliers. The current generator and the main electrodes (source and drain) of the regulating transistor, whose gate is tied to its source, are connected in series across a generator of reference voltage constituted by one or more such multipliers. One of the main electrodes of the regulating transistor is connected, directly or through a further voltage multiplier, to the reference terminal (O) of the controlled circuit while still another such multiplier may be inserted between the ouptut of the constant-current generator and the interconnected source and gate electrodes of the regulating transistor.

Abstract: A binary frequency-divider stage for an electronic wristwatch comprises a set of insulated-gate field-effect transistors (IGFETs) of one and the same conductivity type, one (T.sub.1) of these IGFETs and an associated series capacitor (C.sub.1) forming an amplifier located between one bus bar (M) of a d-c supply and a first one (11) of two a-c control leads carrying a pair of bipolar pulse trains (.PHI..sub.1, .PHI..sub.2) of opposite phase. An incoming pulse sequence (V.sub.E1), of a cadence to be halved, is in phase with the pulse train (.PHI..sub.2) on the other control lead (12) and may be derived directly therefrom (FIG. 5). The gate capacitance of the first IGFET (T.sub.1) can be charged in two steps by a first charging circuit including two IGFETs (T.sub.2, T.sub.3) which are alternately turned on by respective control pulses (.PHI..sub.1, .PHI..sub.2) applied to their gates. A normally blocked discharging circuit, including two other IGFETs (T.sub.4, T.sub.

Abstract: A piezoelectric crystal has an energizing circuit including a low-voltage supply battery connected across two parallel pairs of series-connected field-effect transistors of the insulated-gate type, the junction of each FET pair being tied to a tap of a respective capacitive voltage divider which lies between a reference pole of the battery and a respective terminal of a piezoelectric crystal. Each of these crystal terminals is also connected directly to the gate of the first FET of a respective pair and via a coupling capacitor to the gate of the second FET of the opposite pair, the last-mentioned gate being biased with a potential outside the voltage range of the supply battery.

Abstract: Two pairs of serially connected insulated-gate field-effect transistors (IGFETs) are bridged in parallel across a d-c supply, the junction of the drain and source electrodes of the first pair of IGFETs being tied to the gate of one of the IGFETs of the second pair whose junction is connected to a capacitive load circuit to be periodically energized under the control of at least one train of trigger pulses of low duty ratio applied to the gate of at least one of the IGFETs of the first pair. The gates of the IGFETs of the second pair are alternately triggered through the intermediary of a further IGFET, or pair of serially interconnecred IGFETs, controlling the other IGFET of the second pair.