Patents by Inventor Jakob Raymond Jones
Jakob Raymond Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250021506Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: September 27, 2024Publication date: January 16, 2025Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 12191893Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: GrantFiled: July 26, 2021Date of Patent: January 7, 2025Assignee: ALTERA CORPORATIONInventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Patent number: 12135667Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: May 31, 2023Date of Patent: November 5, 2024Assignee: ALTERA CORPORATIONInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 12038837Abstract: A data processing device incorporates a plurality of chiplets having working elements such as processing and memory elements. At least one of the working elements is operative to generate messages directed to working elements of the same chiplet or another one of the chiplets. Each message includes a global address. An evaluation circuit determines whether the global address of a message is within a range of global addresses assigned to the chiplet. If so, the message passes to a translation circuit which translates the message to a local address for routing to a working element of the chiplet. If not, the message is dispatched to one or more other chiplets.Type: GrantFiled: December 15, 2022Date of Patent: July 16, 2024Assignee: Google LLCInventors: Xi Chen, Chao Ni, Jakob Raymond Jones
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Publication number: 20240202115Abstract: A data processing device incorporates a plurality of chiplets having working elements such as processing and memory elements. At least one of the working elements is operative to generate messages directed to working elements of the same chiplet or another one of the chiplets. Each message includes a global address. An evaluation circuit determines whether the global address of a message is within a range of global addresses assigned to the chiplet. If so, the message passes to a translation circuit which translates the message to a local address for routing to a working element of the chiplet. If not, the message is dispatched to one or more other chiplets.Type: ApplicationFiled: December 15, 2022Publication date: June 20, 2024Inventors: Xi Chen, Chao Ni, Jakob Raymond Jones
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Publication number: 20230305982Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: May 31, 2023Publication date: September 28, 2023Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11693810Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 24, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20220190843Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: ApplicationFiled: July 26, 2021Publication date: June 16, 2022Inventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Publication number: 20220121595Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: December 24, 2021Publication date: April 21, 2022Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11237998Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 22, 2020Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11100029Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: August 8, 2019Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11075648Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: GrantFiled: September 27, 2019Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Patent number: 10831960Abstract: Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.Type: GrantFiled: November 13, 2018Date of Patent: November 10, 2020Assignee: Altera CorporationInventors: Jakob Raymond Jones, Prasanna Padmanabhan
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Publication number: 20200028521Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Inventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Publication number: 20190361831Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: August 8, 2019Publication date: November 28, 2019Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 10445278Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 28, 2016Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 10439639Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.Type: GrantFiled: December 28, 2016Date of Patent: October 8, 2019Assignee: INTEL CORPORATIONInventors: David W. Mendel, Jeffrey Erik Schulz, Keith Duwel, Huy Ngo, Jakob Raymond Jones
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Patent number: 10242141Abstract: A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one event do not occur simultaneously. The logic is included in an event sequencer. The method also includes inserting the event sequencer into the first circuit design during compilation to create a second circuit design and outputting the second circuit design to be implemented on the integrated circuit device.Type: GrantFiled: September 27, 2016Date of Patent: March 26, 2019Assignee: Altera CorporationInventors: Jakob Raymond Jones, Tim Tri Hoang, Ben Chunben Wang
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Patent number: 10127341Abstract: Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.Type: GrantFiled: April 24, 2017Date of Patent: November 13, 2018Assignee: Altera CorporationInventors: Jakob Raymond Jones, Prasanna Padmanabhan
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Patent number: 10102172Abstract: A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.Type: GrantFiled: December 27, 2015Date of Patent: October 16, 2018Assignee: Altera CorporationInventors: Kevin W. Mai, Vishwas Tumkur Vijayendra, Jakob Raymond Jones