Patents by Inventor Jakob Simon

Jakob Simon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11610817
    Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 21, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Kitzler, John Cooper, Jakob Simon Dohr, Michael Knabl, Matic Krivec, Daniel Pieber
  • Patent number: 11597604
    Abstract: Conveyor safety guard modules that are configured to be inserted between adjacent rollers in motor driven roller conveyor systems and shield drive bands or belts coupled between the adjacent rollers so as to protect workers from having their work gloves, loose hair, loose clothing, etc. becoming entangled in the drive bands or belts and causing injury.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: March 7, 2023
    Inventor: Jakob Simon
  • Publication number: 20220301933
    Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: Andreas Kitzler, John Cooper, Jakob Simon Dohr, Michael Knabl, Matic Krivec, Daniel Pieber