Patents by Inventor Jakub Kedzierski
Jakub Kedzierski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10297835Abstract: A glucose fuel cell for reception into a given constrained volume of implantation in a vertebrate in which the glucose fuel cell has access to fluid containing glucose. The fuel cell includes an anode adapted to oxidize the glucose, a cathode adapted to reduce an oxidant, and a membrane disposed between the anode and the cathode and separating the anode from the cathode. At least one of the anode or cathode define a flexible sheet that is geometrically deformed to be receivable into the given constrained volume of implantation and increase volumetric power density. Related methods of making a glucose fuel cell of this type and implantable assemblies including the glucose fuel cell are also disclosed.Type: GrantFiled: May 15, 2014Date of Patent: May 21, 2019Assignee: Massachusetts Institute of TechnologyInventors: Rahul Sarpeshkar, Jeremy Bert Muldavin, Todd Addison Thorsen, Jakub Kedzierski, Benjamin Isaac Rapoport, Michale Sean Fee
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Publication number: 20140342247Abstract: A glucose fuel cell for reception into a given constrained volume of implantation in a vertebrate in which the glucose fuel cell has access to fluid containing glucose. The fuel cell includes an anode adapted to oxidize the glucose, a cathode adapted to reduce an oxidant, and a membrane disposed between the anode and the cathode and separating the anode from the cathode. At least one of the anode or cathode define a flexible sheet that is geometrically deformed to be receivable into the given constrained volume of implantation and increase volumetric power density. Related methods of making a glucose fuel cell of this type and implantable assemblies including the glucose fuel cell are also disclosed.Type: ApplicationFiled: May 15, 2014Publication date: November 20, 2014Inventors: Rahul Sarpeshkar, Jeremy Bert Muldavin, Todd Addison Thorsen, Jakub Kedzierski, Benjamin Isaac Rapoport, Michale Sean Fee
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Patent number: 7859060Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.Type: GrantFiled: August 4, 2009Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Jakub Kedzierski, Raymond M. Sicina
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Patent number: 7816224Abstract: In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.Type: GrantFiled: March 5, 2008Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Jakub Kedzierski, Raymond M. Sicina
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Publication number: 20090289303Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.Type: ApplicationFiled: August 4, 2009Publication date: November 26, 2009Inventors: KEVIN K CHAN, Jakub Kedzierski, Raymond M. Sicina
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Publication number: 20090224320Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.Type: ApplicationFiled: March 5, 2008Publication date: September 10, 2009Inventors: KEVIN K. CHAN, Jakub Kedzierski, Raymond M. Sicina
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Publication number: 20070128785Abstract: A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.Type: ApplicationFiled: February 5, 2007Publication date: June 7, 2007Inventors: CYRIL CABRAL, Meikei Ieong, Jakub Kedzierski
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Publication number: 20070034967Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.Type: ApplicationFiled: October 2, 2006Publication date: February 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hasan Nayfeh, Mahender Kumar, Sunfei Fang, Jakub Kedzierski, Cyril Cabral
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Publication number: 20070001223Abstract: An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.Type: ApplicationFiled: July 1, 2005Publication date: January 4, 2007Inventors: Diane Boyd, Meikei Leong, Jakub Kedzierski, Ghavam Shahidi
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Publication number: 20060240607Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.Type: ApplicationFiled: May 13, 2006Publication date: October 26, 2006Applicant: International Business Machines CorporationInventors: Ying Zhang, Bruce Doris, Thomas Kanarsky, Meikei Jeong, Jakub Kedzierski
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Publication number: 20060189061Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: April 19, 2006Publication date: August 24, 2006Inventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaren Surendra
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Publication number: 20050263831Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: ApplicationFiled: May 4, 2005Publication date: December 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Doris, Diane Boyd, Meikei Ieong, Thomas Kanarsky, Jakub Kedzierski, Min Yang
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Publication number: 20050186747Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: February 25, 2004Publication date: August 25, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Diane Boyd, Cyril Cabral, Richard Kaplan, Jakub Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda Mocuta, Vijay Narayanan, An Steegen, Maheswaran Surendra
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Publication number: 20050127362Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Inventors: Ying Zhang, Bruce Doris, Thomas Kanarsky, Meikei Ieong, Jakub Kedzierski
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Publication number: 20050118757Abstract: A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in fabricating a CMOS structure containing silicide contacts and silicide gate metals.Type: ApplicationFiled: December 2, 2003Publication date: June 2, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Jakub Kedzierski, Victor Ku, Christian Lavoie, Vijay Narayanan, An Steegen
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Publication number: 20050106788Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: ApplicationFiled: December 2, 2004Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky Amos, Katayun Barmak, Diane Boyd, Cyril Cabral, Meikei Leong, Thomas Kanarsky, Jakub Kedzierski
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Publication number: 20050064636Abstract: A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.Type: ApplicationFiled: September 24, 2003Publication date: March 24, 2005Inventors: Cyril Cabral, Meikei Ieong, Jakub Kedzierski