Abstract: A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.

Abstract: A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.

Abstract: A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.

Abstract: Methods, tools and systems for full characterization of thin and ultra-thin layers employed in advanced semiconductor device structures are disclosed.

Abstract: A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.

Abstract: Methods, tools and systems for full characterization of thin and ultra-thin layers employed in advanced semiconductor device structures are disclosed.

Abstract: A deposition method and a system are provided to deposit a CdS buffer layer on a surface of a solar cell absorber layer of a flexible workpiece from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited from the deposition solution while the flexible workpiece is elastically shaped by a series of shaping rollers to retain the process solution on the solar cell absorber layer and while the flexible workpiece is heated by contacting to a heated liquid that the shaping rollers are fully or partially immersed. The flexible workpiece is elastically shaped by pulling a back surface of the flexible workpiece into surface cavity of the shaping rollers using magnetic force.

Abstract: Described in one embodiment is a system that has a multiple number of different stations for forming solar cell modules. Described in another embodiment is a system that includes a cutting station, a setting station, and an interconnection station to create different series-connected flexible solar cell modules. Described in still another embodiment is a monolithically integrated multi-module power supply.

Abstract: The present inventions generally relate to thin film solar cell fabrication, and more particularly, to techniques for interconnecting solar cells based on Group IBIIIAVIA thin film semiconductors. In a particular embodiment, a system is described that positions solar cells and conductive leads with respect to each other so that application of a conductive adhesive and formation of an assembled solar cell string, followed by curing and cooling of the conductive adhesive, can occur in a repeatable manner.

Abstract: A deposition method and a system are provided to deposit a CdS buffer layer on a surface of a solar cell absorber layer of a flexible workpiece from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited from the deposition solution while the flexible workpiece is heated and elastically shaped by a heated shaping plate to retain the process solution on the solar cell absorber layer. The flexible workpiece is elastically shaped by pulling a back surface of the flexible workpiece into a cavity area in the heated shaping plate using an attractive force.

Abstract: A deposition method and a system are provided to deposit a CdS buffer layer on a surface of a solar cell absorber layer of a flexible workpiece from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited from the deposition solution while the flexible workpiece is elastically shaped by a series of shaping rollers to retain the process solution on the solar cell absorber layer and while the flexible workpiece is heated by contacting to a heated liquid that the shaping rollers are fully or partially immersed. The flexible workpiece is elastically shaped by pulling a back surface of the flexible workpiece into surface cavity of the shaping rollers using magnetic force.

Abstract: The present inventions generally relate to thin film solar cell fabrication, and more particularly, to techniques for interconnecting solar cells based on Group IBIIIAVIA thin film semiconductors. In a particular embodiment, a system is described that positions solar cells and conductive leads with respect to each other so that application of a conductive adhesive and formation of an assembled solar cell string, followed by curing and cooling of the conductive adhesive, can occur in a repeatable manner.

Abstract: A deposition method and a system are provided to deposit a CdS buffer layer on a surface of a solar cell absorber layer of a flexible workpiece from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited from the deposition solution while the flexible workpiece is heated and elastically shaped by a heated shaping plate to retain the process solution on the solar cell absorber layer. The flexible workpiece is elastically shaped by pulling a back surface of the flexible workpiece into a cavity area in the heated shaping plate using an attractive force.

Abstract: A roll-to-roll or reel-to-reel RTP tool including a reactor having a continuous insert placed in a primary gap of the reactor is provided. The primary gap of the reactor is defined by peripheral reactor walls including a top reactor wall, a bottom reactor wall and side reactor walls. The continuous insert includes a continuous process gap through which a continuous workpiece travels between an entry opening and an exit opening of the insert. An inner space exists between at least one of the insert walls and at least a portion of the peripheral reactor walls that make up the primary gap. At least one gas inlet is connected to the inner space, and at least one exhaust opening connects the process gap as well as the inner space to outside the reactor and carries any gaseous products to outside the process gap and the primary gap of the reactor.

Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.

Abstract: An apparatus for electropolishing a conductive layer on a wafer using a solution is disclosed. The apparatus comprises an electrode assembly immersed in the solution configured proximate to the conductive layer having a longitudinal dimension extending to at least a periphery of the wafer, the electrode assembly including an elongated contact electrode configured to receive a potential difference, an isolator adjacent the elongated contact electrode, and an elongated process electrode adjacent the isolator configured to receive the potential difference, a voltage supply is configured to supply the potential difference between the contact electrode and the process electrode to electropolish the conductive layer on the wafer.

Abstract: A roll to roll rapid thermal processing tool which is used to react a precursor material disposed over a flexible foil substrate to form a solar cell absorber. The RTP tool includes a significantly low aspect ratio process gap through which a flexible foil substrate is moved. A low temperature zone of the RTP tool forms a first portion of the process gap, a high temperature zone of the RTP tool forms a second portion of the process gap, and a buffer zone forms a third portion of the process gap that connects the first portion to the second portion of the gap. The temperature of a section of the flexible foil substrate is increased from the temperature of the low temperature zone to the temperature of the high temperature zone as the section of the continuous workpiece travels through the buffer zone. The buffer zone includes at least one low thermal conductivity section having cavities.

Abstract: A carrier head for holding a workpiece during processing of a workpiece surface is provided. The carrier head includes a carrier housing, a base and a pressure member. The base is configured to hold the workpiece and is movable with respect to the carrier housing. The pressure member is between the base and the carrier housing and is configured to induce the base to apply a predetermined force onto the process surface.

Abstract: A semiconductor substrate rinsing method and apparatus. A wet processed substrate is spun to reduce the amount of process solution on the surface of the substrate. The concentration of the process solution on the surface of the substrate is reduced by applying a cleaning solution to the surface. The cleaning solution may be applied from nozzles on a supply member positioned across from the surface of the substrate. The nozzles may be angled to evenly distribute application of the cleaning solution on the substrate.

Abstract: An integrated process tool for chemical mechanical processing, cleaning and drying a semiconductor workpiece is provided. The integrated process tool includes a CMP module and a cleaning and drying module. After being processed, the workpiece is transported from the CMP module to the cleaning and drying module using a movable housing. In the cleaning and drying module, a cleaning mechanism is used to clean the workpiece while the workpiece is rotated and held by a support stucture of the movable housing. A drying mechanism of the cleaning and drying module picks up the workpiece from the moveable housing and spin dries it. Throughout the CMP process, cleaning and drying, the processed surface of the wafer faces down.