Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: An enhancement mode metal insulator semiconductor high electron mobility transistor (HEMT) is presented herein. By using a polarization stack to replace the traditional barrier layer, a thinner barrier layer (e.g., a thinner layer of AlGaN) may be formed during fabrication to effectuate a low-sheet-resistance two-dimensional electron gas. Advantageously, the thinner (.i.e., less-than-ten nanometers) barrier layer mitigates reactive ion etching (RIE) induced surface damage. This in turn allows the formation of a recessed gate. Additionally, a dual dielectric gate stack may be deposited to further reduce leakage currents and to improve subthreshold slope.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.