Abstract: A method and apparatus are provided to divide a logical to physical table into multiple parts, one part in a first fast memory and a second part in a second non-volatile memory, wherein an algorithm may be used in the division.

Abstract: Technology is described herein that provides a partial reset of a non-volatile memory controller. In one aspect, a non-volatile memory controller persists memory addresses of I/O queues across a partial reset of the non-volatile memory controller. The non-volatile memory controller may also persist a mapping between each I/O submission queue and a corresponding I/O completion queue across the partial reset. Persisting the addresses of the I/O queues and/or mappings alleviates the need for a host system and non-volatile memory controller to perform a lengthy process of sharing the addresses of the I/O queues and/or mappings.

Abstract: A method and apparatus are provided to divide a logical to physical table into multiple parts, one part in a first fast memory and a second part in a second non-volatile memory, wherein an algorithm may be used in the division.

Abstract: Technology is described herein that provides a partial reset of a non-volatile memory controller. In one aspect, a non-volatile memory controller persists memory addresses of I/O queues across a partial reset of the non-volatile memory controller. The non-volatile memory controller may also persist a mapping between each I/O submission queue and a corresponding I/O completion queue across the partial reset. Persisting the addresses of the I/O queues and/or mappings alleviates the need for a host system and non-volatile memory controller to perform a lengthy process of sharing the addresses of the I/O queues and/or mappings.

Abstract: An apparatus having a memory and a controller is disclosed. The memory may have a write head and sectors in tracks. The controller may have a sector map and a translation map and may be configured to (i) receive a write command having a logical block address and a range value, (ii) examine the sector map to find a sector sequence (a) marked free, (b) about to reach the write head and (c) at least as long as the range value, (iii) write new data in the sector sequence, (iv) update the translation map to associate the logical block address of the write command with a physical address of the written sectors and (v) update the sector map according to the sectors written. Each entry in the sector map generally corresponds to a respective sector and indicates whether the respective sector contains valid data or is free.

Abstract: A memory system and method for fast firmware download are provided. In one embodiment, a memory system is presented comprising non-volatile memory, volatile memory, and a controller. The controller is configured to receive a boot loader and firmware; store the boot loader and firmware in the volatile memory; execute the boot loader, wherein executing the boot loader causes the controller to read the firmware from the volatile memory, decompress the firmware, and store the decompressed firmware in the volatile memory; and copy the compressed firmware from the volatile memory to the non-volatile memory. Other embodiments are provided.

Abstract: An apparatus having a memory and a controller is disclosed. The memory may have a write head and sectors in tracks. The controller may have a sector map and a translation map and may be configured to (i) receive a write command having a logical block address and a range value, (ii) examine the sector map to find a sector sequence (a) marked free, (b) about to reach the write head and (c) at least as long as the range value, (iii) write new data in the sector sequence, (iv) update the translation map to associate the logical block address of the write command with a physical address of the written sectors and (v) update the sector map according to the sectors written. Each entry in the sector map generally corresponds to a respective sector and indicates whether the respective sector contains valid data or is free.

Abstract: Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance zones exhibit different performance criteria for one or more of: reading data from the storage device and writing data to the storage device. The storage controller is further adapted to allocate storage from each of the plurality of performance zones for each of the plurality of logical volumes such that the performance criteria for accessing the storage device is distributed substantially uniformly across the plurality of logical volumes.

Abstract: Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance zones exhibit different performance criteria for one or more of: reading data from the storage device and writing data to the storage device. The storage controller is further adapted to allocate storage from each of the plurality of performance zones for each of the plurality of logical volumes such that the performance criteria for accessing the storage device is distributed substantially uniformly across the plurality of logical volumes.