Patents by Inventor James A. Beavens

James A. Beavens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrating intellectual property (IP) blocks into a processor
    Patent number: 9021156
    Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 28, 2015
    Inventors: Prashanth Nimmala, Robert J. Greiner, Lily P. Looi, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens, Aimee D. Wood, Jeff V. Tran
  • Integrating Intellectual Property (IP) Blocks Into A Processor
    Publication number: 20130054845
    Abstract: In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: Prashanth Nimmala, Robert J. Greiner, Lily P. Looi, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens, Aimee D. Wood, Jeff V. Tran
  • Method and system for efficient cache memory updating with a least recently used (LRU) protocol
    Patent number: 6643742
    Abstract: A method of and system for concurrently processing multiple memory requests. The first and second memory requests contain a linear address. A search for the cache entry in a cache block is issued in response to the linear address. After locating the cache entries associated with the memory requests, there is an update of the least recently used status for the cache entries with reference to the memory requests.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: November 4, 2003
    Assignee: Intel Corporation
    Inventors: Rohit Vidwans, James A. Beavens