Patents by Inventor James A. Boyd

James A. Boyd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220114086
    Abstract: Examples include techniques to expand system memory via use of available device memory. Circuitry at a device coupled to a host device partitions a portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload. The partitioned portion of memory capacity is reported to the host device as being available for use as a portion of system memory. An indication from the host device is received if the portion of memory capacity has been identified for use as a first portion of pooled system memory. The circuitry to monitor usage of the memory capacity used by the compute circuitry to execute the workload to decide whether to place a request to the host device to reclaim the memory capacity from the first portion of pooled system memory.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Chace A. CLARK, James A. BOYD, Chet R. DOUGLAS, Andrew M. RUDOFF, Dan J. WILLIAMS
  • Publication number: 20210232504
    Abstract: A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 29, 2021
    Inventors: James A. BOYD, Christopher E. COX, Nikhil TALPALLIKAR
  • Publication number: 20210089225
    Abstract: Examples described herein relate to a device comprising a controller, a volatile memory device, and a non-volatile memory device. In some examples, the controller is to allocate an amount of the volatile memory device based on an amount of energy available to the device during a failure event. In some examples, the amount of energy available to the device during a failure event comprises watts over an amount of time. In some examples, the failure event comprises one or more of: power reduction, power loss, voltage reduction or loss, current reduction or loss, global reset, machine check, operating system (OS) failure or crash. In some examples, the allocated amount of the volatile memory device comprises a number of bytes. In some examples, the controller is to: indicate an amount of energy to copy data from the volatile memory device to the non-volatile memory device and receive an indication of the amount of energy available to the volatile memory device for a failure event.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 25, 2021
    Inventor: James A. Boyd
  • Patent number: 10956323
    Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Dale J. Juenemann, James A. Boyd, Robert J. Royer, Jr.
  • Patent number: 10949356
    Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: James A. Boyd, Robert J. Royer, Jr., Lily P. Looi, Gary C. Chow, Zvika Greenfield, Chia-Hung S. Kuo, Dale J. Juenemann
  • Patent number: 10866737
    Abstract: Techniques and mechanisms for exchanging information between a solid state drive (SSD) and a write-in-place non-volatile memory via a host device. In an embodiment, access control information defines state of the SSD, where the access control information determines and/or is based on an access by the host device to other non-volatile memory of the SSD. The access control information includes address conversion information defining a correspondence of a logical address with a physical address for a location of the other non-volatile memory of the SSD. At least some of the access control information is stored by the SSD to the write-in-place non-volatile memory for later retrieval by the SSD. In another embodiment, the SSD signals that a commit operation is to be performed to flush any cached or buffered access control information into the write-in-place non-volatile memory.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Anand S. Ramalingam, James A. Boyd, Myron Loewen
  • Patent number: 10540505
    Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: James A. Boyd, Dale J. Juenemann, Robert J. Royer, Jr.
  • Patent number: 10482010
    Abstract: An embodiment of a memory apparatus may include a persistent host memory buffer, and a memory controller communicatively coupled to the persistent host memory buffer to control communication between the persistent host memory buffer and a persistent storage media device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: James A. Boyd, John W. Carroll, Sanjeev N. Trika
  • Publication number: 20190303300
    Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.
    Type: Application
    Filed: June 14, 2019
    Publication date: October 3, 2019
    Inventors: James A. BOYD, Robert J. ROYER, JR., Lily P. LOOI, Gary C. CHOW, Zvika GREENFIELD, Chia-Hung S. KUO, Dale J. JUENEMANN
  • Publication number: 20190251023
    Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.
    Type: Application
    Filed: January 15, 2019
    Publication date: August 15, 2019
    Inventors: James A. BOYD, Dale J. JUENEMANN, Francis R. CORRADO
  • Publication number: 20190102565
    Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: INTEL CORPORATION
    Inventors: JAMES A. BOYD, DALE J. JUENEMANN, ROBERT J. ROYER, JR.
  • Patent number: 10204039
    Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: James A. Boyd, Dale J. Juenemann, Francis R. Corrado
  • Publication number: 20190042414
    Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.
    Type: Application
    Filed: May 10, 2018
    Publication date: February 7, 2019
    Inventors: Dale J. JUENEMANN, James A. BOYD, Robert J. ROYER, JR.
  • Publication number: 20190042415
    Abstract: A processor is described. The processor includes register space to accept input parameters of a software command to move a data item out of computer system storage and into persistent system memory. The input parameters include an identifier of a software process that desires access to the data item in the persistent system memory and a virtual address of the data item referred to by the software process.
    Type: Application
    Filed: June 12, 2018
    Publication date: February 7, 2019
    Inventors: James A. BOYD, Dale J. JUENEMANN
  • Publication number: 20190026226
    Abstract: A disclosed example to manage intermittently connectable storage media includes a cache initializer to initialize a nonvolatile cache corresponding to an intermittently connectable storage media device connected to a host system; a cache flush manager to change a cache flush mode associated with the nonvolatile cache from a cache write through mode to a cache write back mode based on the intermittently connectable storage media device being disconnected from the host system; a cache access manager to maintain the nonvolatile cache after the intermittently connectable storage media device is disconnected, and in response to a data access request corresponding to the intermittently connectable storage media device, perform a corresponding data access operation using the nonvolatile cache.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Inventors: James A. Boyd, Dale J. Juenemann
  • Publication number: 20190004940
    Abstract: An embodiment of a memory apparatus may include a persistent host memory buffer, and a memory controller communicatively coupled to the persistent host memory buffer to control communication between the persistent host memory buffer and a persistent storage media device. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: James A. Boyd, John W. Carroll, Sanjeev N. Trika
  • Publication number: 20170371785
    Abstract: Examples include techniques for a write commands to one or more storage devices coupled with a host computing platform. In some examples, the write commands may be responsive to write requests from applications hosted or supported by the host computing platform. A tracking table is utilized by elements of the host computing platform and the one or more storage devices such that the write commands are completed by the one or more storage devices without a need for an interrupt response to elements of the host computing platform.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Applicant: Intel Corporation
    Inventors: James A. Boyd, John W. Carroll, Sanjeev N. Trika, Mark A. Schmisseur
  • Publication number: 20170351452
    Abstract: In one embodiment, dynamic host memory buffer allocation in accordance with the present description includes sensing a level of activity of a memory or storage and dynamically allocating a portion of a host memory as a buffer to the non-volatile memory, as a function of a sensed level of activity of the non-volatile memory. Such dynamic allocation of host memory buffers as a function of sensed levels of activity, can improve the efficiency of the allocation of memory resources and improve system performance. Other aspects are described herein.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Inventors: James A. BOYD, John W. CARROLL, Sanjeev N. TRIKA
  • Patent number: 9690503
    Abstract: A controller maintains exposed and unexposed locations of a first storage device and a second storage device. In response to receiving a request a perform a write operation to write data in locations that span the first storage device and the second storage device, the controller atomically writes an entirety of the data in the unexposed locations of the first storage device.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 27, 2017
    Assignee: INTEL CORPORATION
    Inventors: James A. Boyd, Scott E. Burridge
  • Publication number: 20170083454
    Abstract: Techniques and mechanisms for exchanging information between a solid state drive (SSD) and a write-in-place non-volatile memory via a host device. In an embodiment, access control information defines state of the SSD, where the access control information determines and/or is based on an access by the host device to other non-volatile memory of the SSD. The access control information includes address conversion information defining a correspondence of a logical address with a physical address for a location of the other non-volatile memory of the SSD. At least some of the access control information is stored by the SSD to the write-in-place non-volatile memory for later retrieval by the SSD. In another embodiment, the SSD signals that a commit operation is to be performed to flush any cached or buffered access control information into the write-in-place non-volatile memory.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Anand S. Ramalingam, James A. Boyd, Myron Loewen