Abstract: A system and method for implementing a flexible interrupt mechanism in an electronic system includes a processor that may initially execute an initialization routine for performing an interrupt configuration procedure. The foregoing interrupt configuration procedure may preferably be initiated when the processor programs a configuration register with certain selectable interrupt parameters that may be utilized to flexibly configure an interrupt module in the electronic system. Internal and external interrupt sources may then subsequently provide various interrupts to the configured interrupt module which may responsively detect and route the interrupts to the processor based upon interrupt information provided during the foregoing interrupt configuration procedure. The processor may then effectively service the interrupts during appropriate interrupt servicing procedures by utilizing corresponding interrupt handler routines.

Abstract: A system and method for implementing a flexible interrupt mechanism in an electronic system includes a processor that may initially execute an initialization routine for performing an interrupt configuration procedure. The foregoing interrupt configuration procedure may preferably be initiated when the processor programs a configuration register with certain selectable interrupt parameters that may be utilized to flexibly configure an interrupt module in the electronic system. Internal and external interrupt sources may then subsequently provide various interrupts to the configured interrupt module which may responsively detect and route the interrupts to the processor based upon interrupt information provided during the foregoing interrupt configuration procedure. The processor may then effectively service the interrupts during appropriate interrupt servicing procedures by utilizing corresponding interrupt handler routines.

Abstract: A system and method for efficiently performing a data transfer operation in an electronic system preferably includes a processor that may initially create a DMA structure in a block transfer memory device. The DMA structure may preferably include one or more command structures for performing DMA data transfer operations. The processor may subsequently program local control registers of a DMA engine with selected DMA transfer information in response to a DMA data transfer requirement. The processor may then instruct the DMA engine to perform the required DMA data transfer operation. Next, the DMA engine may responsively copy one or more of the command structures from the block transfer memory device into local command registers that are coupled to the DMA engine. The DMA engine may then reference the foregoing control registers and command registers to thereby efficiently perform one or more DMA data transfer operations.