Abstract: A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.

Abstract: A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry.

Abstract: A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.

Abstract: A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

Abstract: An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in association with a monitored path. The sense circuit includes a variable delay element coupled to a controller. A data signal from the monitored path is provided to the sense circuit which adds an amount of delay as determined by the controller to the data signal. The delayed data signal and the original data signal are compared to determine if their values match. If they match, then the amount of delay added by the variable delay element is increased. If they do not match, then a previous amount of delay, prior to the mismatch, is output as the slack of the monitored path. The slack may then be used to tune the speed of the integrated circuit.

Abstract: Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering is enabled for the device memory address ranges. Transfer operations are processed to transfer data to contiguous device memory addresses in the device. A determination is made as to whether the indicator bits for the contiguous device memory addresses indicate that gathering is enabled. A single bus I/O transaction is generated to transfer data for the contiguous device memory addresses over the I/O bus in response to determining that the indicator bits for the contiguous device memory addresses indicate that gathering is enabled.

Abstract: A novel roof vent in accordance with the present invention, utilizes a vent pipe communicating with a shroud, where the shroud compatibly fits over a ridge vent on a roof. The vent pipe is extended above the roof, sufficiently so as to rise above the anticipated level of snow load that may be experienced in the locale of the application. The roof vent of the preferred embodiment includes an apron that adjustably fits the roof pitch of the installation and further includes a ridge vent cutout for compatibly fitting over the ridge vent. In one version of the present invention, cosmetic dress may be used to allow the roof vent to blend with architectural requirements without impacting the functionality of the roof vent operation.

Abstract: A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

Abstract: Methods, data processing systems, and program products are disclosed that support the definition and accessing of links indicating a relationship between configuration construct instances, such as Dial and Dial group instances, within a digital design. According to one method, first and second latches within the digital design are specified in at least one HDL statement within one or more HDL files representing the digital design. In the one or more HDL files, a first configuration construct instance referencing the first latch and a second configuration construct instance referencing the second latch are also defined. The first and second configuration construct instances provide interfaces through which values of the first and second latches can be accessed. In addition, a link indicating a relationship between the first and second configuration construct instances is also defined within the one or more HDL files.

Abstract: An embryo transfer catheter or other medical device has a shaft extruded with two layers. The outer layer is relatively thick and contains gas bubbles sufficient to increase the visibility of the catheter under ultrasound observation but with a density that allows material within the catheter to be viewed by the eye. The inner layer is relatively thin and is free of bubbles so that it provides a smooth bore to the catheter.

Abstract: The invention provides methods and kits to form water swellable gel coatings, preferably lubricious coatings, on substrates, and coated substrates thus formed. The coatings contain one or more antimicrobial metals formed with atomic disorder, together with one or more antimicrobial metals formed with atomic disorder such that the coatings provide an antimicrobial and anti-inflammatory effect when wet. The invention also provides a method to produce metal powders by sputtering a coating onto a moving surface, and then scraping the coating with one or more scrapers to produce the metal powder. The method is particularly useful for producing large amounts of nanocrystalline antimicrobial metal powders formed with atomic disorder, useful in the water swellable gel coatings of this invention.

Abstract: A closed system suction catheter has a catheter enclosed within a flexible envelope secured between a patient end fitting and a machine end fitting. The patient end fitting has a cleaning chamber with a valve at its patient side and is normally closed so that the cleaning chamber is isolated from the patient. The valve has an outer rigid housing enclosing a one-piece elastomeric moulding of tubular shape. The elastomeric moulding has two pads projecting externally through openings in the outer housing. The elastomeric moulding also has a web extending internally across its diameter with a diametrically-extending slit aligned with the pads. A collar mounted on the housing is slidable along the housing to engage the pads so as to apply pressure across the web and open the slit, thereby allowing the catheter to be advanced to the patient.

Abstract: The invention provides an aerogel-hollow particle binder composition comprising an aqueous binder, hydrophobic aerogel particles, and hollow, non-porous particles, as well as an insulation composite comprising the aerogel-hollow particle binder composition, and a methods of preparing the aerogel-hollow particle binder composition and insulation composite.

Abstract: The invention provides methods and kits to form water swellable gel coatings, preferably lubricious coatings, on substrates, and coated substrates thus formed. The coatings contain one or more antimicrobial metals formed with atomic disorder, together with one or more antimicrobial metals formed with atomic disorder such that the coatings provide an antimicrobial and anti-inflammatory effect when wet. The invention also provides a method to produce metal powders by sputtering a coating onto a moving surface, and then scraping the coating with one or more scrapers to produce the metal powder. The method is particularly useful for producing large amounts of nanocrystalline antimicrobial metal powders formed with atomic disorder, useful in the water swellable gel coatings of this invention.

Abstract: An epidural catheter with a soft tip is formed by extruding a two-layer tube where the inner layer is stiffer than the outer layer. The inner layer is then removed, such as by machining, from a short length at the tip, which is subsequently end-formed closed and a side opening cut into it.

Abstract: The invention provides a heat resistant aerogel insulation composite comprising an insulation base layer comprising hydrophobic aerogel particles and an aqueous binder, and a thermally reflective top layer comprising a protective binder and an infrared reflecting agent. The invention also provides a method of preparing a heat resistant aerogel insulation composite, as well as methods of preparing an aerogel binder composition and aerogel binder compositions so prepared.

Abstract: An embryo transfer catheter has a main lumen, which opens close to the patient end through a side opening. The catheter is extruded with a second, smaller lumen, which is closed at both ends. The second lumen is filled with air so that it reflects ultrasound energy and enhances the visibility of the catheter under ultrasound observation.