Abstract: This present invention relates to a modifiable, removable rack insert for an interior section of a cooler or ice chest. The rack insert supports game meat, fish and other items above the base of the cooler, thereby allowing dirt, grass and other debris to keep separate from the items stored on the rack. Additionally, the rack insert surface facilitates proper drainage of liquid and other debris therefrom so that the items stored thereon are not in contact with the same for extended periods of time. The modified rack insert is adjustable in size and can accommodate different sized coolers as per the requirements of its user.

Abstract: Furniture configurable between a display configuration and a storage configuration that eases transport and storage and reduces the furniture footprint. The furniture includes an upper region that has seating and a backrest, and a lower region that is below the upper region and adapted to engage a support surface beneath the furniture when in the display configuration. In combination, the upper and lower regions define at least first and second sections of the furniture that are coupled by at least one hinge so that the first section comprises a first portion of the upper region and a first portion of the lower region and the second section comprises a second portion of the upper region and a second portion of the lower region, and the at least one hinge is configured so that the first and second sections pivot toward each other when the furniture is in the storage configuration.

Abstract: This present invention relates to a modifiable, removable rack insert for an interior section of a cooler or ice chest. The rack insert supports game meat, fish and other items above the base of the cooler, thereby allowing dirt, grass and other debris to keep separate from the items stored on the rack. Additionally, the rack insert surface facilitates proper drainage of liquid and other debris therefrom so that the items stored thereon are not in contact with the same for extended periods of time. The modified rack insert is adjustable in size and can accommodate different sized coolers as per the requirements of its user.

Abstract: Furniture configurable between a display configuration and a storage configuration that eases transport and storage and reduces the furniture footprint. The furniture includes an upper region that has seating and a backrest, and a lower region that is below the upper region and adapted to engage a support surface beneath the furniture when in the display configuration. In combination, the upper and lower regions define at least first and second sections of the furniture that are coupled by at least one hinge so that the first section comprises a first portion of the upper region and a first portion of the lower region and the second section comprises a second portion of the upper region and a second portion of the lower region, and the at least one hinge is configured so that the first and second sections pivot toward each other when the furniture is in the storage configuration.

Abstract: This invention relates to adaptively compensating for variations in integrated chip circuitry due to delays caused by multiple thresholds. The multi-threshold adaptive dynamic scaling system disclosed compensates for normal on-chip variations which affect system process and voltage variability, as well as overall performance. This system regulates a voltage control and provides high voltage thresholds, regular voltage thresholds, and low voltage thresholds to compensate for threshold voltage variations.

Abstract: A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.

Abstract: A method for and an apparatus in which the FSOURCE connection in a fuse domain is split into multiple nets, allowing flexible placement of primary fuses in the floorplan, is provided. In particular, multiple FSOURCE connections (e.g. C4 pads or wire pads) are provided in the floorplan, allowing flexible placement of primary fuses without additional overhead.

Abstract: An electronic device packaging assembly (10) that includes a ball grid array (60) and specialized construction to be able to operate from DC up to 50 GHz with minimal parasitic losses. The packaging assembly (10) includes a thin base plate (14) made of a suitable rigid material. Power vias (48), signal vias (26) and ground vias (46) are formed through the base plate (14) to be coupled to traces, circuit components, and/or the device (12) within the packaging assembly (10). An impedance matching compensation network (28) provides impedance matching between the device (12) and the signal vias (26). The ball grid array (60) includes a plurality of solder balls (68), including ground solder balls (72), signal solder balls (74) and power solder balls (76), electrically coupled to the appropriate via extending through the base plate (14).

Abstract: An electronic device packaging assembly (10) that includes a ball grid array (60) and specialized construction to be able to operate from DC up to 50 GHz with minimal parasitic losses. The packaging assembly (10) includes a thin base plate (14) made of a suitable rigid material. Power vias (48), signal vias (26) and ground vias (46) are formed through the base plate (14) to be coupled to traces, circuit components, and/or the device (12) within the packaging assembly (10). An impedance matching compensation network (28) provides impedance matching between the device (12) and the signal vias (26). The ball grid array (60) includes a plurality of solder balls (68), including ground solder balls (72), signal solder balls (74) and power solder balls (76), electrically coupled to the appropriate via extending through the base plate (14).

Abstract: A method and system for performing fault tolerant static timing analysis for an electronic network. A composite timing graph is generated by making K+1 copies of the zero-defect timing graph of the network, where K is a predetermined maximum number of defects present on a path of the network, and static timing analysis is performed on the composite timing graph.

Abstract: A process for fabricating a photonics package includes securing a ferrule to an optical fiber, inserting the ferrule through a movable flange into a photonics housing containing a photodiode, adjusting the ferrule longitudinally within the flange to position the end of the optical fiber with respect to the surface of the photodiode and welding the ferrule to the flange. Thereafter, the ferrule and flange assembly is adjusted laterally with respect to the photodiode and the lower end of the flange is secured to the housing using hot gas injection or laser soldering which allows lateral adjustment of the fiber during the solder cooling process for final positioning with respect to the photodiode.

Abstract: A process for fabricating a photonics package includes securing a ferrule to an optical fiber, inserting the ferrule through a movable flange into a photonics housing containing a photodiode, adjusting the ferrule longitudinally within the flange to position the end of the optical fiber with respect to the surface of the photodiode and welding the ferrule to the flange. Thereafter, the ferrule and flange assembly is adjusted laterally with respect to the photodiode and the lower end of the flange is secured to the housing using hot gas injection or laser soldering which allows lateral adjustment of the fiber during the solder cooling process for final positioning with respect to the photodiode.

Abstract: A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

Abstract: A method and system for performing fault tolerant static timing analysis for an electronic network. A composite timing graph is generated by making K+1 copies of the zero-defect timing graph of the network, where K is a predetermined maximum number of defects present on a path of the network, and static timing analysis is performed on the composite timing graph.

Abstract: A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

Abstract: An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.

Abstract: An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.