Abstract: A method of holographic recording in a photorefractive medium wherein stored holograms may be retrieved with maximum signal-to noise ratio (SNR) is disclosed. A plurality of servo blocks containing position feedback information is recorded in the crystal and made non-erasable by heating the crystal. The servo blocks are recorded at specific increments, either angular or frequency, depending whether wavelength or angular multiplexing is applied, and each servo block is defined by one of five patterns. Data pages are then recorded at positions or wavelengths enabling each data page to be subsequently reconstructed with servo patterns which provide position feedback information. The method of recording data pages and servo blocks is consistent with conventional practices. In addition, the recording system also includes components (e.g.

Abstract: A clock generation circuit includes a reference clock for putting out a stable reference clocking signal. A digital ring oscillator includes a series circuit loop having at least one inverting gate and a programmable delay line of plural delays formed a series of tapped digital transmission gates connected between an output and an input of the inverting gate. A multiplexer selects among the series of taps in accordance with a tap selection signal. A clock monitoring circuit is connected to compare the clock output with a stable reference clocking signal to produce a digital clock cycle count. A programmed microcontroller generates the tap selection value as a function of the digital clock cycle count and a desired clock output frequency set point.

Abstract: An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.