Patents by Inventor James A. Kahle
James A. Kahle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190250918Abstract: A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
-
Patent number: 10296339Abstract: A system and process for managing thread transitions includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A determination is made whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets. Responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, a portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the one or more threads.Type: GrantFiled: August 11, 2018Date of Patent: May 21, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
-
Patent number: 10152450Abstract: According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.Type: GrantFiled: August 13, 2012Date of Patent: December 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dong Chen, Noel A. Eisley, Philip Heidelberger, James A. Kahle, Fabrizio Petrini, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
-
Publication number: 20180349141Abstract: A system and process for managing thread transitions includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A determination is made whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets. Responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, a portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the one or more threads.Type: ApplicationFiled: August 11, 2018Publication date: December 6, 2018Inventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
-
Patent number: 10120810Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: GrantFiled: December 1, 2017Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
-
Patent number: 10055226Abstract: A system and process for managing thread transitions includes determining that a transition is to be made regarding the relative use of two data register sets where the two data register sets are used by a processor as first-level registers for thread execution. Based on the transition determination, a determination is made whether to move thread data in at least one of the first-level registers to second-level registers. Responsive to determining to move the thread data, a portion of main memory or cache memory is assigned as the second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing a thread. The thread data from the at least one first-level register is moved to the second-level registers based on the move determination.Type: GrantFiled: July 2, 2017Date of Patent: August 21, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
-
Patent number: 10049061Abstract: Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred.Type: GrantFiled: November 12, 2012Date of Patent: August 14, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, James A. Kahle, Jaime H. Moreno, Ravi Nair
-
Publication number: 20180089093Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: ApplicationFiled: December 1, 2017Publication date: March 29, 2018Inventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
-
Patent number: 9910783Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: GrantFiled: February 3, 2017Date of Patent: March 6, 2018Assignee: International Business Machines CorporationInventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
-
Publication number: 20170300331Abstract: A system and process for managing thread transitions includes determining that a transition is to be made regarding the relative use of two data register sets where the two data register sets are used by a processor as first-level registers for thread execution. Based on the transition determination, a determination is made whether to move thread data in at least one of the first-level registers to second-level registers. Responsive to determining to move the thread data, a portion of main memory or cache memory is assigned as the second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing a thread. The thread data from the at least one first-level register is moved to the second-level registers based on the move determination.Type: ApplicationFiled: July 2, 2017Publication date: October 19, 2017Inventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
-
Patent number: 9782000Abstract: Disclosed is an adjustable rack. In example embodiments, the rack may include a rail enclosing a nut used to fix a holder to the rail.Type: GrantFiled: May 23, 2016Date of Patent: October 10, 2017Inventors: James Kahle, Mary Kahle
-
Patent number: 9703561Abstract: Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.Type: GrantFiled: May 11, 2014Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
-
Publication number: 20170161200Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: ApplicationFiled: February 3, 2017Publication date: June 8, 2017Inventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
-
Patent number: 9582427Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: GrantFiled: August 31, 2015Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
-
Publication number: 20160338489Abstract: Disclosed is an adjustable rack. In example embodiments, the rack may include a rail enclosing a nut used to fix a holder to the rail.Type: ApplicationFiled: May 23, 2016Publication date: November 24, 2016Inventors: James Kahle, Mary Kahle
-
Publication number: 20150370719Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
-
Patent number: 9218291Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.Type: GrantFiled: July 25, 2013Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
-
Patent number: 9197920Abstract: Embodiments of the present invention provide a method, system and computer program product for providing a shared user experience during media playback. In an embodiment of the invention, a method for providing a shared user experience during media playback is provided. The method includes selecting for a particular user a media file for playback in a media player executing in memory by a processor of a computer. The method also includes retrieving a shared user experience audio file recorded for a different user during a previous playback of the selected media file. Finally, the method includes playing back for the particular user both the selected media file and the retrieved shared user experience audio file concurrently in the media player.Type: GrantFiled: October 13, 2010Date of Patent: November 24, 2015Assignee: International Business Machines CorporationInventors: Travis M. Grigsby, James A. Kahle, Michael A. Paolini
-
Patent number: 9064030Abstract: Embodiments relate to tree traversal in a memory device. An aspect includes a method for tree traversal in a memory device. The method includes receiving a pointer to a tree structure within memory of the memory device. An evaluation condition is received to identify a desired node of the tree structure. The tree structure is traversed to identify the desired node. Data is returned from the desired node meeting the evaluation condition.Type: GrantFiled: November 29, 2012Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: James A. Kahle, Jaime H. Moreno, Ravi Nair
-
Patent number: 9037669Abstract: According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.Type: GrantFiled: August 9, 2012Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Dong Chen, Noel A. Eisley, Philip Heidelberger, James A. Kahle, Fabrizio Petrini, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara