Abstract: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280) over a first portion of the base electrode layer, a portion of the first portion of the emitter electrode and a portion of the semiconductor substrate; and (d) implanting a dopant into a second portion of the base electrode layer after forming the emitter electrode after forming the mask layer.

Abstract: A method is provided for forming bipolar (103) and MOS (105) semiconductor devices in a common substrate (46), comprising, forming a combination comprising an MOS device (105) in a first region (44) of the substrate (46) and a portion (50) of a collector region (82, 64, 62, 50) of the bipolar device (103) in a second portion (42) of the substrate (46), covering the MOS device (105) with differentially etchable dielectric layers (56, 58) and the combination with an etch-stop layer (68), completing formation of the bipolar device (103) without completely removing the etch-stop layer (68) from the MOS device (105), anisotropically etching the differentially etchable layers (56, 58) to form a gate sidewall (56?, 58?) of the MOS device (105), and applying contact electrodes (98) to the MOS (105) and bipolar (103) devices.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: A method of manufacturing a semiconductor component includes: providing a semiconductor substrate (210, 510); forming a trench (130, 430) in the semiconductor substrate to define a plurality of active areas separated from each other by the trench; forming a buried layer (240, 750) in the semiconductor substrate underneath a portion of the trench, where the buried layer is at least partially contiguous with the trench; after forming the buried layer, depositing an electrically insulating material (133, 810) in the trench; forming a collector region (150, 950) in one of the plurality of active areas, where the collector region forms a contact to the buried layer; forming a base structure over the one of the plurality of active areas; and forming an emitter region over the one of the plurality of active areas.

Abstract: A method of manufacturing a semiconductor component includes: providing a semiconductor substrate (210, 510); forming a trench (130, 430) in the semiconductor substrate to define a plurality of active areas separated from each other by the trench; forming a buried layer (240, 750) in the semiconductor substrate underneath a portion of the trench, where the buried layer is at least partially contiguous with the trench; after forming the buried layer, depositing an electrically insulating material (133, 810) in the trench; forming a collector region (150, 950) in one of the plurality of active areas, where the collector region forms a contact to the buried layer; forming a base structure over the one of the plurality of active areas; and forming an emitter region over the one of the plurality of active areas.

Abstract: An integrated circuit that supports digital circuits, analog circuits, and RF circuits on a single IC. Digital CMOS circuitry lies on a low resistivity layer that provides good latch-up qualities and allows for dense PAD I/O. Analog CMOS circuitry rests on an isolated well region on a highly resistive layer in order to minimize signal crosstalk through the substrate. Analog BJT devices also sit on a highly resistive region within its own well structure in order to minimize parasitic capacitances and provide for high frequency device switching. RF passive elements, such as inductors and capacitors, rest on a highly resistive region in order to minimize signal losses that especially occur at high frequencies. RF active components rest on a highly resistive region to maximize device performance.

Abstract: A method of manufacturing a heterojunction BiCMOS IC. (100) includes forming a gate electrode (121, 131), forming a protective layer (901, 902) over the gate electrode, forming a semiconductor layer (1101) over the protective layer, depositing an electrically insulative layer (1102, 1103) over the semiconductor layer, using a mask layer (1104) to define a doped region (225) in the semiconductor layer and to define a hole (1201) in the electrically insulative layer, forming an electrically conductive layer (1301) over the electrically insulative layer, using another mask layer (1302) to define an emitter region (240) in the electrically conductive layer and to define an intrinsic base region (231) and a portion of an extrinsic base region (232) in the electrically conductive layer, and using yet another mask layer (1502) to define another portion of the extrinsic base region in the electrically conductive layer.

Abstract: A method of fabricating a semiconductor structure having MOS and bipolar devices includes providing an isolation structure having MOS and bipolar active areas including doped wells. A collector region is formed in the bipolar active area well and a first semiconductor layer is then formed over the MOS and bipolar active areas. An active base region is formed in the bipolar active area well and a dielectric layer is formed on the first semiconductor layer over a portion of the bipolar active area. A window is formed through the dielectric layer and extends to the first semiconductor layer. A second semiconductor layer is then formed over the MOS and bipolar active areas. A gate electrode is formed on the MOS active area and emitter and collector electrodes are formed on the bipolar active area. The gate, emitter and collector electrodes are formed from both the first and second semiconductor layers and the emitter electrode extends into the window.

Abstract: An improved method of fabricating a high performance bipolar and MOS integrated circuit is provided. The method utilizes a single polysilicon layer, a self-aligned emitter-base structure, self-aligned silicide contacts, and silicon dioxide sidewall spacers to obtain reduced emitter and base resistance, reduced collector to base capacitance, greater switching speed, and a higher packing density. The method also has the advantage of being simple and compatible with a method of fabricating MOS devices which improves performance and yield.

Abstract: A method for making a bipolar semiconductor device having silicide contacts which is compatible with the processing steps used in the fabrication of MOS devices. The present invention includes the use of sidewall spacers to limit the self-aligned implants of the extrinsic base and the silicide contact. The device is annealed so that the diffusion of the polysilicon layer which forms the emitter may be controlled. Since the emitter size may be controlled, the emitter to base contact area may be reduced resulting in improved device performance.