Abstract: The performance of a Very Large Scale Integrated Read-Only Memory Circuit is improved by providing an architecture for columns of memory cells so that a signal from an addressed memory cell need propagate on diffusion bit lines by a distance approximately equal to the length of the diffusion bit line within a single block of memory cells. The architecture of the memory layout is improved by providing bit line and virtual ground line contacts at opposing ends of the memory block and by replicating the memory block through mirror symmetry on the semiconductor substrate. The memory array is further improved by providing bank selection transistors for each bank at each opposing end of a memory block so the propagation signal of an addressed memory cell need only travel the length of a single bit diffusion line in the bank.

Abstract: In a logic cell, a plurality of gates are serially connected and responsive to signals on a plurality of conductors to perform a particular logic function. The gates are responsive to subsystem clock signals which control the operation of the gates to delay the output of the logic cell. The cell includes at least one ratioless gate, and at least one ratioed gate. The ratioless gates provide high speed and reduced size, while the ratioed gates provide low noise characteristics. In combination, the ratioed gates, which provide strong output signals, make excellent drivers for the ratioless gates which are particularly adapted to accommodate complex logic networks.