Abstract: A photofinishing apparatus is designed such that full bleed durable prints are produced with a high productivity and low waste generation process. The photofinishing apparatus in this case includes a printer and a finisher or post-print treatment processor. The printer is designed to produce media segment with multiple images of various formats. This media segment is then transported to the post-print treatment processor. The post-print treatment processor includes a dryer station, a durability station, a two-axis cutting station, and a print sorting station. The dryer performs the function of drying the media segment. The durability station performs the function of applying and or fixing durability material on the media segments. The two-axis cutting station includes slitting and chopping stations that performs the required two-axis cutting that produces the full bleed prints.

Abstract: A reliable, low cost system for generating precisely aligned pixel clock and index signals for a digital scanning or printing system is based on the use of a phase locked loop multiplier to generate a sampling clock precisely synchronized to the drum position encoder sensor output. The sample clock frequency is chosen to be a large, known multiple M of the pixel clock frequency. The pixel clock is chosen to be the sample clock divided by M, making it the proper frequency. Pixel clock phase is established by resetting, on the trailing edge of an index signal generated by a line start index sensor, a .div.M counter used in deriving the pixel clock from the sample clock. The rising edge of the pixel clock is then established to within .+-.(1/M) pixel clock periods of the trailing edge of the index signal.

Abstract: A reliable, low cost system for generating precisely aligned pixel clock and index signals for a digital scanning or printing system is based on a novel single channel encoder pattern detected with a single sensor. The signal output of the sensor representing the encoder pattern is processed with phase locked loop based circuit to generate pixel clock and index signals of known and guaranteed phase.