Patents by Inventor James A. McCall

James A. McCall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RECONFIGURABLE CLOCKING ARCHITECTURE
    Publication number: 20170243627
    Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventors: Mozhgan Mansuri, Aaron Martin, James A. McCall
  • METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION
    Publication number: 20170237431
    Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 17, 2017
    Inventors: James A. McCALL, Kuljit S. BAINS
  • Techniques to Access or Operate a Dual In-Line Memory Module via Multiple Data Channels
    Publication number: 20170199830
    Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
    Type: Application
    Filed: June 28, 2016
    Publication date: July 13, 2017
    Inventors: Bill Nale, Kuljit S. Bains, George Vergis, Christopher E. Cox, James A. McCall, Chong J. Zhao, Suneeta Sah, Pete D. Vogt, John R. Goles
  • Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines
    Patent number: 9665527
    Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Christopher P Mozak, James A McCall, Bryan K Casper
  • MULTIPLE RANK HIGH BANDWIDTH MEMORY
    Publication number: 20170140809
    Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 18, 2017
    Applicant: Intel Corporation
    Inventors: Christopher P. Mozak, Randy B. Osborne, Michael Gutzmann, James A. McCall
  • Method and apparatus for dynamic memory termination
    Patent number: 9595963
    Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: James A McCall, Kuljit S Bains
  • Method of manufacturing a circuit board
    Patent number: 9596766
    Abstract: A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: David N. Shykind, James A. McCall
  • Apparatus, method and system for determining reference voltages for a memory
    Patent number: 9552164
    Abstract: Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: James A. McCall, Kuljit S. Bains
  • Memory device specific self refresh entry and exit
    Publication number: 20160350002
    Abstract: A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.
    Type: Application
    Filed: December 26, 2015
    Publication date: December 1, 2016
    Inventors: George Vergis, Kuljit S. Bains, James A. McCall, Murugasamy K. Nachimuthu, Mohan J. Kumar
  • LOW SWING VOLTAGE MODE DRIVER
    Publication number: 20160285451
    Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.
    Type: Application
    Filed: October 5, 2015
    Publication date: September 29, 2016
    Inventors: JAMES A. MCCALL, KULJIT S. BAINS, DEREK M. CONROW, AARON MARTIN
  • IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA
    Publication number: 20160284386
    Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: James A. McCall, Kuljit S. Bains
  • Mapping memory controller connectors to memory connectors
    Patent number: 9384164
    Abstract: Provided are a device, system, and method for mapping memory controller connectors to memory connectors. A memory is programmed to transmit for each of a plurality of the memory data connectors, a pattern on the memory data connectors that has a first value for a selected memory data connector of the memory data connectors and a different value from the first value for the memory data connectors other than the selected memory data connector. For each of the memory data connectors, a read command is issued to read the pattern on the memory data connectors. a device data connector receiving the first value in the read pattern is mapped to the selected memory data connector transmitting the first value.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 5, 2016
    Assignee: INTEL CORPORATION
    Inventors: Kuljit S. Bains, James A. Mccall
  • I/O driver transmit swing control
    Patent number: 9374004
    Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Christopher P. Mozak, Ritesh B. Trivedi, James A. McCall, Aaron Martin
  • ADJUSTABLE LOW SWING MEMORY INTERFACE
    Publication number: 20160162214
    Abstract: A memory device interface with a programmable driver. The memory device is associated with a memory controller, with one or more input/output (I/O) signal lines coupled between the memory device and the memory controller. The memory device includes an I/O signal line interface including a driver for each I/O signal line. The driver is a programmable driver to dynamically adjust an output voltage swing for transmission via the I/O signal line interface.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 9, 2016
    Inventors: James A McCall, Christopher P Mozak
  • DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL
    Publication number: 20160162434
    Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 9, 2016
    Inventors: Christopher P. Mozak, James A. McCall, Bryan K. Casper
  • Dual-Sensory Eyewear Device
    Publication number: 20160103339
    Abstract: A dual-sensory eyewear device for providing visual and aural distractions. The dual-sensory eyewear device includes a frame to which a pair of voltage controlled liquid crystal display lenses and audio devices may be connected. An electronics system and a power system are also included and are housed within the frame. The power system provides electrical current while the electronics package dictates operation of the lenses and the audio devices. Display drivers of the electronics package allow the pair of lenses to switch between an opaque and transparent state, while an audio amplifier operates the pair of speakers. Operation commands to dictate use of the pair of lenses and the pair of speakers can be remotely transmitted to the electronics package through a wireless communication module and interpreted through a signal decoder.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Inventors: Benjamin L. White, Russell J. Gulotta, Charles Lewis, Daryl James McCall Evans
  • COMMON DIE IMPLEMENTATION FOR MEMORY DEVICES
    Publication number: 20160092383
    Abstract: A memory device and a memory controller can interface over a system data bus that has a narrower bandwidth than a data bus internal to the memory device. The memory device and memory controller transfer data over the system data bus on all transfer periods of a burst length, but send fewer bits than would be needed for the exchange to transfer all bits that can be read or written on the internal data bus of the memory device. The memory device can have different operating modes to allow for a common memory device to be used in different system configurations based on the ability to interface with the narrower bandwidth system data bus.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Kuljit S. Bains, Nadav Bonen, Christopher E. Cox, James A. McCall
  • METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION
    Publication number: 20160065212
    Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 3, 2016
    Inventors: James A. McCall, Kuljit S. Bains
  • Apparatus and method to reduce power delivery noise for partial writes
    Patent number: 9240250
    Abstract: Apparatus, systems, and methods to reduce power delivery noise for partial writes are described. In one embodiment, an apparatus comprises a processor and a memory control logic to insert one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 19, 2016
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, James A. McCall, Pete D. Vogt, Michael Gutzmann
  • Periodic training for unmatched signal receiver
    Patent number: 9218575
    Abstract: I/O parameters are adjusted based on a number of errors detected in a received training signal. A controller device sends the training signal while a memory device is in a training mode. The memory device samples the training signal and the system causes an adjustment to at least one I/O parameter based on a detected number of errors. Either the controller or the memory device can perform the error detection, depending on the configuration of the system. Either an I/O parameter of the controller or an I/O parameter of the memory device can be adjusted, depending on the configuration of the system.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 22, 2015
    Assignee: Intel Corporation
    Inventors: Christopher P. Mozak, James A. McCall