Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.

Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register.

Abstract: An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.

Abstract: A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

Abstract: Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction.

Abstract: A wireless communications device includes a receiver, and a demodulator coupled downstream from the receiver and configured to use a continuous phase modulation (CPM) waveform to non-coherently demodulate a received signal. The demodulator is configured to generate waveform banks, each waveform bank having a respective different frequency offset associated therewith, determine a correlation output metric for each waveform bank, select a waveform bank for demodulating the received signal based upon the correlation output metrics of the waveform banks, and demodulate the received signal using the selected waveform bank and the associated frequency offset.

Abstract: A processor architecture to qualify software target-branch hints with hardware-based predictions, the processor including a branch target address cache having entries, where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction, the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction; and if there is a match, depending upon the state value stored in the entry, the processor will use the stored target address as the predicted target address for the decoded indirect branch instruction, or will use a software provided target address hint if available.

Abstract: An indexing system for graph data. In particular implementations, the indexing system provides for denormalization and replica index functionality to improve query performance.

Abstract: Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.

Abstract: Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media are disclosed. In this regard, a method for processing instructions in a central processing unit (CPU) is provided. The method comprises decoding an instruction comprising a plurality of bits, and generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. If the parity error indicator indicates that the parity error exists in the plurality of bits, one or more of the plurality of bits are modified to indicate a no execution operation (NOP), without effecting a roll back of a program counter of the CPU and without re-decoding the instruction. In this manner, the possibility of the parity error causing an inadvertent execution of an unpredictable instruction is reduced.

Abstract: The invention provides the compounds of formula (): and pharmaceutically acceptable salts thereof, wherein R1, R2, R3, R4, A, X, Y, a, b and n are as defined herein. Also disclosed are methods for making the compounds of formula (I) and their use in treating or preventing diseases associated with cell overproliferation and dysfunctional sphingolipid signal transduction. The invention also encompasses the use of the compounds in combination with an apoptosis-signaling ligand, such as Fas ligand. Preferably, the Fas ligand is administered in the form of a gene therapy agent.

Abstract: The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.

Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Abstract: Systems and methods are disclosed for maintaining an instruction cache including extended cache lines and page attributes for main cache line portions of the extended cache lines and, at least for one or more predefined potential page-crossing instruction locations, additional page attributes for extra data portions of the corresponding extended cache lines. In addition, systems and methods are disclosed for processing page-crossing instructions fetched from an instruction cache having extended cache lines.

Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. in this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.

Abstract: An indexing system for graph data. In particular implementations, the indexing system provides for denormalization and replica index functionality to improve query performance.

Abstract: A Block Normal Cache Allocation (BNCA) mode is defined for a processor. In BNCA mode, cache entries may only be allocated by predetermined instructions. Normal memory access instructions (for example, as part of interrupt code) may execute and will retrieve data from main memory in the event of a cache miss; however, these instructions are not allowed to allocate entries in the cache. Only the predetermined instructions (for example, those used to establish locked cache entries) may allocate entries in the cache. When the locked entries are established, the processor exits BNCA mode, and any memory access instruction may allocate cache entries. BNCA mode may be indicated by setting a bit in a configuration register.

Abstract: A wireless communications device may include a receiver configured to receive a continuous phase modulation (CPM) signal and a demodulator coupled downstream from the receiver. The demodulator may be configured to generate a CPM correlation matrix based upon an expected CPM signal, and generate a temporary correlation matrix. The temporary correlation matrix may include a first copy of the CPM correlation matrix inverted in time, and a second copy of the CPM correlation matrix.

Abstract: The present invention relates to a geographic information system having editable maps. In an embodiment, a system provides editable maps. The system includes an edit layer dataset that stores geocoded data. At least a portion of the edit layer dataset is edited by a user. The system also includes a base layer dataset that includes trusted geocoded data and a moderation module that receives a change in the edit layer dataset. The moderation module determines whether the change is reliable and promotes the change in the edit layer dataset to the base layer dataset if the change is reliable.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.