Abstract: One variation of a method includes: detecting a first location of a user carrying a mobile pack proximal a first scan zone; accessing a first sequence of images representing trees in the first scan zone; characterizing a first coverage density of the first scan zone based on visual features detected in the first sequence of images; in response to the first coverage density exceeding a threshold coverage density, alerting the user of scan completion; detecting a second location of the user proximal a second scan zone; accessing a second sequence of images representing trees in the second scan zone; characterizing a second coverage density of the second scan zone based on visual features detected in the second sequence of images; and, in response to the second coverage density falling below the threshold coverage density, prompting the user to increase a traversal speed for a third scan zone.

Abstract: GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a transmit portion and a receive portion, the analog portions adaptable to interface with an analog network. The transceiver is first configured to operate in a test mode. In the test mode, the transmit portion of the digital processing section is activated to generate data to be transmitted by the transmit portion of the analog section. The receive portion of the analog section and the receive portion of the digital processing section are operated to receive data. Thereafter, the parametrics of select portions of the receive portion of the digital processing section are examined during the receipt of data by the receive portion of the analog section and processing thereof by the receive portion of the digital processing section.

Abstract: Method and apparatus for configuring the operation of an integrated circuit. An integrated circuit with external programming capabilities is disclosed. A pin current source is provided for interfacing with at least one pin on the integrated circuit to control current flow there through to an external load interfaced to the at least one pin external to the integrated circuit. The external load has at least two discrete values. A voltage detector detects the voltage on the at least one pin and a state detector then compares the voltage on the at least one pin to at least two discrete voltage thresholds. Each of the discrete voltages is associated with a separate value of a control word, and the state detector is operable to determine the value of the control word associated with the detected voltage. The state detector then outputs the determined value of the control word.

Abstract: On-chip calibrated source termination for voltage mode driver. An amplifier is disclosed having an internal amplifier with a first output and a second output, the first output interfaced to a non-inverting input through an interface. The second output is coupled to the first output through a series resistance element. The output impedance of the amplifier is determined by the ratio of the current drive of the first and second outputs. The voltage on said second output being a function of said interface and the current input to said internal amplifier.

Abstract: Switching node regulator for sfp ethernet adaptor. A method is disclosed for regulating voltage on an integrated circuit formed on a substrate to power circuitry on the substrate. An unregulated power supply is provided as an input to the integrated circuit connected between a positive node and a reference node on the integrated circuit. Current is sourced in a first current sourcing step through drive circuitry on the substrate from the positive node to an inductor/capacitor reactive circuit external to the integrated circuit. The output of the inductor/capacitor reactive circuit comprises a filtered regulated power supply voltage that is operable to power at least a portion of the circuitry on the substrate. Current is sourced in a second current sourcing step through the drive circuitry on the substrate from the reference node to the inductor/capacitor reactive circuit when the current in the inductor is ramping down.

Abstract: Multi-channel line interface unit with on-chip clock management. A method for clocking a multi-channel Line Interface Unit (LIU) embodied in an integrated circuit and having a plurality of channels is disclosed. Each channel has a receive path and a transmit path. An reference clock input is provided for receiving an external reference clock signal. A free running on-chip clock is generated that is synchronized to the reference clock signal. On at least two of the channels, transmit or receive data clocks and associated corresponding transmit and receive data operating at an associated data rate are received. Transmit and receive data are processed on each of the respective channels with a portion of the processing occurring in the digital domain.

Abstract: On-chip calibrated source termination for voltage mode driver. An amplifier is disclosed having an internal amplifier with a first output and a second output, the first output interfaced to a non-inverting input through an interface. The second output is coupled to the first output through a series resistance element. The output impedance of the amplifier is determined by the ratio of the current drive of the first and second outputs. The voltage on said second output being a function of said interface and the current input to said internal amplifier.

Abstract: Integrated circuit with junction temperature sensing diode. An integrated circuit with temperature sensing capabilities is disclosed. The integrated circuit includes a substrate for containing circuitry on the surface thereof. At least one section of the circuitry on the surface of the substrate is operable, during a normal operating mode, to raise the surface temperature of the substrate. A sensing element is disposed within the at least one section for sensing temperature varying parameters that vary as a function of temperature.

Abstract: Output driver for high speed Ethernet transceiver. A transmission line driver is disclosed for driving a transmission line in a first operating mode and in a second operating mode. The first and second operating modes operate substantially exclusive of each other. A current driver is provided for driving the transmission line in the first operating mode from a first data generator and at a first output voltage. A voltage driver is provided for driving the transmission line in the second operating mode from a second data generator at a second output voltage through a load, such that the current driver and the voltage driver operate independent of each other.

Abstract: Output driver for high speed Ethernet transceiver. A transmission line driver is disclosed for driving a transmission line in a first operating mode and in a second operating mode. The first and second operating modes operate substantially exclusive of each other. A current driver is provided for driving the transmission line in the first operating mode from a first data generator and at a first output voltage. A voltage driver is provided for driving the transmission line in the second operating mode from a second data generator at a second output voltage through a load, such that the current driver and the voltage driver operate independent of each other.

Abstract: A technique for compensating for supply voltage variations in a delay circuit by utilizing a bias circuit to maintain the delay substantially constant with respect to the supply voltage. The bias circuit generates a bias current having a fixed component and a variable component, in which the variable component varies proportionately to variations in the supply voltage to maintain the delay substantially constant.

Abstract: Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.

Abstract: Socket contact (10) has cantilever arms (16) which are stamped without blanking any strip stock from therebetween, each pair of arms (16) being framed with transition portions 24) which diverge from the axis of the terminal (10) to provide space between facing sheared edges (18, 20). A centerline spacing of 0.109 inches in strip form is achieved. Furthermore, a contact (10) insertion feature (150) for applying an insertion force to insert the contact (10) into a terminal receiving passage (124) of an electrical connector without causing the contact (10) to skive the interior surface of the passage (124). A portion of retaining plate (29) is formed out of the plane thereof to define a vertical surface (151) facing opposite the direction of insertion of contact (10). The insertion feature (50) is formed early in the formation of contact (10); vertical surface (151) is used as a reference from which the outer features of contact (10) are referenced.

Abstract: This invention relates to terminal contacts for electrical connectors and in particular one aspect of the invention relates to socket contacts formed in strip on close centerline spacing and another aspect of the invention relates to an insertion feature to facilitate insertion of terminal contacts into an electrical connector housing.

Abstract: An electrical connector assembly (12, 17) including means (17) for securing the connector assembly to a printed circuit board (11). The electrical connector housing (12) has an eyelet (17) disposed in an aperture (12b) in a mounting flange (12c) in an interference fit. The eyelet (17) has a flange (21) engaging the mounting flange (12c) of the housing (12), an inverted conical end (18b; 30b) remote from the flange (21) and a generally tubular shank (20, 23; 32, 30) extending therebetween. A first section (20) of the shank provides the interference fit with the aperture (12b). A second section (23) of the shank extends below the mounting flange for disposition within an aperture (11a) in the printed circuit board (11). The second section (23) may be tapered or of a smaller diameter than the first section (20).