Abstract: An apparatus can include a coupler for coupling a robotic arm to a surgical table having a table top on which a patient can be disposed. The coupler can include a first portion configured to couple to a surgical table and a second portion configured to couple to a robotic arm. The second portion may include a post that may translate into the first portion. The first portion may comprise a locking mechanism having one or more stages to constrain movement of the second portion relative to the first portion in six degrees of freedom. The coupler can thus provide secure coupling of the robotic arm to the surgical table.

Abstract: A method for manufacturing a current collector for an electrode of a battery cell includes forming the current collector using a metal 3D printing process; defining L layers of the current collector, where L is an integer greater than zero during the 3D printing of the current collector; and defining a lattice structure in at least one of the L layers of the current collector during the 3D printing of the current collector.

Abstract: Described herein are compounds of Formula I: and their pharmaceutically acceptable salts, wherein R1, R2, R3, L1, T1, T2, T3, T4, t1, and t2 are defined herein; their use as GIPR antagonists; pharmaceutical compositions containing such compounds and salts; and the use of such compounds and salts to treat or prevent, for example, obesity, weight gain, and/or T2DM.

Abstract: A first speed sensor interface is operatively connected to a first time-space partition of a processor. A second speed sensor interface is operatively connected to a second time-space partition of the processor. A high side control is operatively connected to the first time-time space partition to receive a discrete command from the first time-space partition, and to receive a serial command from the first time-space partition. A low side control is operatively connected to the second time-time space partition to receive a discrete command from the second time-space partition, and to receive a serial command from the second time-space partition. The high side control and the low side control are configured to connect to an outside fuel shutoff device in manner that requires consensus between the high side control and the low side control to control the fuel shutoff device to shutoff fuel flow.

Abstract: A diffuser for positioning in an opening of a passageway having conditioned air, the diffuser including a grate assembly, a pan assembly, and a retention assembly. The grate assembly includes an upper portion and a lower portion. The upper portion contains an aperture, a plurality of slotted sections, and a flange. The lower portion includes downwardly depending sidewalls and a stop. The pan assembly includes a tray with an aperture and a plurality of upwardly depending legs. The retention assembly couples the grate assembly with the pan assembly and contains a first member that is movable from a first position to a second position for selectively engaging the stop.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: A diffuser for positioning in an opening of a passageway having conditioned air, the diffuser including a grate assembly, a pan assembly, and a retention assembly. The grate assembly includes an upper portion and a lower portion. The upper portion contains an aperture, a plurality of slotted sections, and a flange. The lower portion includes downwardly depending sidewalls and a stop. The pan assembly includes a tray with an aperture and a plurality of upwardly depending legs. The retention assembly couples the grate assembly with the pan assembly and contains a first member that is movable from a first position to a second position for selectively engaging the stop.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.

Abstract: A floor terminal for positioning in a passageway in a raised floor system having conditioned air. The floor terminal includes an air delivery system, a damper coupled to the air delivery system, and a grate assembly coupled to the air delivery system. The air delivery system includes a pair of sidewalls, a back, a bottom, a bracket and a baffle, wherein the baffle is selectively coupled between the pair of sidewalls. The damper is selectively coupled to the air delivery system. The damper includes a vane positioned between a frame and a motor in a housing, wherein the motor moves the vane between a first position and a second position to selectively vary the flow of air through the damper. The grate assembly fits within the bracket to couple the grate assembly with the air delivery system to mount the air delivery system and the damper within the passageway and to position the air delivery system within the hole in the floor.

Abstract: A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

Abstract: Disclosed herein is a shaped charge assembly for use in a perforating gun. The shaped charge assembly includes a shaped charge combined with a longitudinal spine extending along a portion of a perforating gun barrel. The shaped charge can be secured to the spine with a retaining shell. A bushing is included between the outer radius of the casing the retaining shell. The bushing serves to absorb shock during detonation of the shaped charge and to help in orienting the shaped charges.

Abstract: A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bits. The failed bit indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.