Abstract: A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.

Abstract: In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.

Abstract: A heating, ventilation, and air conditioning (HVAC) system uses unvitiated secondary return air to control the amount of a contaminant, such as carbon dioxide, in a space to maintain an improved air quality throughout the area served by the system. Preferably a terminal box controls the CO.sub.2 level in the space served by the box by selectively drawing air representative of air in other rooms to lower the CO.sub.2 level in the space being served. This reduces cost because air which is provided from other rooms within the building will require less total system heating or cooling in order to maintain the occupied space at the desired air quality.

Abstract: An information handling system, having a programmable clocking system for clocking data in and out of a processor, includes a processor, having one or more buses connected thereto, wherein a processor clock, and a clock for each of the buses connected to the processor, may be operating at different clock rates relative to each other, the programmable clocking circuit for generating bus clock signals with predetermined cycle skew eliminates the need to distribute separate clock signals across the processor chip. The clock generation circuit uses signals available on the processor integrated circuit for functional operation and tests. Further, flush and hold signals control predetermined latches in the clock generator circuit.

Abstract: A method and system for the enhanced efficiency of data transfers from memory to multiple processors in a data processing system. Each of the multiple processors has an associated buffer for storing data transferred via a common bus which couples the processors and memory together. Each of the multiple processors continually monitors the common bus and is capable of asserting a selected control signal in response to an attempted activity of another one of the multiple processors which would violate data coherency within the data processing system during a particular period of time following the attempted activity. Data is transferred from memory to a buffer associated with one of the multiple processors and stored in the buffer in response to a request from the processor associated with the buffer prior to expiration of the particular period of time and prior to a determination of whether or not this transfer will result in a possible data coherency problem.

Abstract: Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches. A directory field entry provides an indication of whether or not a particular cache line in the L1 cache is also included in the L2 cache.

Abstract: Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.

Abstract: An air conditioning unit is provided with a high capacity filtration system for removing pollutants from supply air, typically return air which has been recirculated from the conditioned area. A filter bypass passage and suitable flow control devices are provided so that supply air, typically fresh outdoor air, may be routed around the filtration system when minimal or no filtration is required. An air quality detector samples the air quality and positions the flow control devices to effect the most cost efficient operation of the air handling unit under the given operating conditions.

Abstract: Atomic memory references require a data processing system to present the appearance of a coherent memory system, which may be achieved in most multiprocessor systems by means of normal memory coherency systems. Writes or attempted writes to memory must be monitored by a processor in order to correctly resolve hits against the reservation state. In a two level cache system the second level cache filters bus operations and forwards to the processor any bus traffic that may involve data stored within the first level cache. This may be accomplished by enforcing an "inclusion" property wherein all data entries within the first level cache are required to be maintained within higher level caches. A problem arises when a block within a first level cache which has had a reservation pending is cast out and the second level cache no longer forwards bus traffic to the associated processor, despite the continued pendency of the reservation.

Abstract: A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, an operation request package is transmitted to a second device from a first device, which informs the second device of the total amount of data to be transferred. A transfer signal is then transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device.

Abstract: An air conditioning unit is provided with a high capacity filtration system for removing pollutants from supply air, typically return air which has been recirculated from the conditioned area. A filter bypass passage and suitable flow control devices are provided so that supply air, typically fresh outdoor air, may be routed around the filtration system when minimal or no filtration is required. An air quality detector samples the air quality and positions the flow control devices to effect the most cost efficient operation of the air handling unit under the given operating conditions.

Abstract: An air conditioning unit is provided with a high capacity filtration system for removing pollutants from supply air, typically return air which has been recirculated from the conditioned area. A filter bypass passage and suitable flow control devices are provided so that supply air, typically fresh outdoor air, may be routed around the filtration system when minimal or no filtration is required. An air quality detector samples the air quality and positions the flow control devices to effect the most cost efficient operation of the air handling unit under the given operating conditions.

Abstract: The desirable features of self powered air distribution terminals and electronic controls are combined by providing an interface between the electronic controls and one or more self powered terminal units in an air distribution system. The electronic controls monitor temperatures and other conditions and provide electric signals each having a voltage which represents the difference between the sensed condition and a set condition entered into the system microprocessor. The interface may be an electro-pneumatic transducer or a set of solenoid valves. The interface responds to the electric signals by applying proportional pressure signals to one or more terminal units. The flow of conditioned air into the area or areas served by the system is then adjusted to conform the actual conditions with the set conditions.