Abstract: A first battery assembly is in a first battery housing that is mechanically engageable with a portable computer, and a second battery assembly is in a second battery housing that is mechanically couplable to the first battery housing. A switch has a first configuration in which communication is established between the portable computer and the first battery assembly and a second configuration in which communication is established between the portable computer and the second battery assembly.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: Methods and apparatus to upgrade and control information presented to process plant operators are disclosed. A disclosed example method to control information presented to a process plant operator comprises presenting a first version of a process plant display, presenting a dynamic attention user interface when a selectable element of the first version of the process plant operator display is activated, wherein the dynamic attention user interface is to be used to adjust an importance of information presented in the first version of the process plant display, and presenting a second version of the process plant display based on a variable adjusted via the dynamic attention user interface.

Abstract: In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

Abstract: The present invention extends to methods, systems, and computer program products for location based messaging. A user at one computer system selects at least on other computer system that is to receive an electronic message. The at least one other computer system is selected based on the location of the at least one other computer system, without having to know an electronic identifier of any users at the at least one other computer system. The computer system refers to a mapping that maps computer systems locations to corresponding electronic addresses. Messages can then be sent to the electronic addresses. Accordingly, embodiments of the present invention facilitate at least semi-anonymous electronic communication in a network computing environment and significantly mitigate the perceived need of an immediate response that is often associated with responding to (potentially in person) verbal communication.

Abstract: Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration.

Abstract: A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

Abstract: In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

Abstract: An apparatus for providing tactile feedback to an operator. The apparatus includes first and second magnetic assemblies having first and second magnets, respectively. The apparatus further includes a user input device, such as a trigger, a knob, a release cord, or a joystick, that is connected to at least one of the two assemblies and positions the first magnet proximate to the second magnet such that interaction occurs between the magnetic fields to generate a force that is exerted on the input device. The force may be an opposing, resisting, or attractive force that creates movement of the user input such as resisting a triggering or releasing action in an interactive video game when the poles are of like polarity. The first magnetic assembly may be stationary, and the second magnetic assembly may be connected to the user input device to be positioned relative to the first magnet assembly.

Abstract: A system, method, and computer program for design validation, comprising defining a plurality of requirements; extracting said plurality of requirements; comparing a design against said plurality of requirements; and reporting a result of said comparison, and appropriate means and computer-readable instructions.

Abstract: A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

Abstract: A circuit board on which the electronic components providing power to a series of light sources is positioned as near as possible to light sources in order to minimize parasitic energy losses which would be introduced by lengths of wiring. The light sources are usually elongate tubular Cold Cathode Fluorescent Tubes arranged parallel to one another in a single plane and the circuit board may be mounted directly over the light sources, towards one end of the tubes. Standard PCB board-to-board connectors may be provided at an edge of the circuit board and a further circuit board provided with a series of conductive tracks may provide both a mechanical and electrical connection between the circuit board and the light sources. A power distribution method is also disclosed in which both current and temperature of the light sources are monitored and regulated in order to extend the lifetime of the light sources and to stabilize their brightness.

Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: An improved time-to-first-fix (TTFF) for GPS systems is provided through a comparison of the time-of-week (TOW) to the sub-frame identification (ID). In one embodiment, this comparison comprises dividing the TOW to form a ratio and performing a modulus operation on the ratio to form a remainder, which is then incremented. If the incremented remainder equals the sub-frame ID, the TOW is assumed to be valid, thereby providing a time of transmission. The time of transmission may then be used to calculate pseudoranges and determine a receiver's location.

Abstract: A method and apparatus are provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the transmitter terminates communications, drops the common mode level with the idle input being activated.