Abstract: A method for minimizing ECC bits in variable sized data formats is provided that comprises determining the number of ECC bits needed for each of a plurality of data formats and creating a common data representation for using a single implementation of error detection and correction logic for all of the plurality of data formats. The method then chooses an ECC matrix and default values for unused data bits in the common data representation such that any ECC bits beyond the minimum required for that sized data format will have known values thereby allowing smaller data formats to go through the error detection and correction logic using the common data representation. The method then retrieves a data entry having one of the plurality of data formats and formats the data entry into the common data representation.

Abstract: A method for controlling memory page migration in a parallel processor computer (10) is provided that comprises requesting access to a memory page (14) by a requester processor (206). The method then determines whether the requester processor (206) is a local processor or a remote processor. The method then increments a local access counter (52) and identifies the local access counter (52) as an incremented counter in response to determining that the requester processor (206) is a local processor. If the requester processor (206) is determined to be a remote processor, the method increments a remote access counter (54) and identifies the remote access counter (54) as the incremented counter. The method next sets a threshold processing indicator to a positive value if the incremented counter exceeds a value threshold (58) or if a difference between the local access counter (52) and the remote access counter (54) exceeds a difference threshold (62).

Abstract: A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer (10) having a plurality of processor regions and a plurality of memory pages (16). Each processor region includes one or more processors (12). Each processor (12) includes a cache (18), and each memory page (16) includes one or more cache lines (20) for coupling to the cache (18) of processors (12) within the plurality of processor regions using the memory page (16). Each memory page (16) includes a set of protection bits (82) associated with each processor region in the plurality of processor regions. The set of protection bits (82) includes an acquire protection bit (84) for each processor region in the plurality of processor regions. The acquire protection bit (84) determines whether the associated processor is enabled to perform acquire operations on the memory page (16).