Abstract: Various embodiments of transdermal patch disposal devices are disclosed. Each such disposal device utilizes a containment having a patch disposal slot. A transdermal patch may be directed through this patch disposal slot for retention within an internal chamber of the containment. This patch disposal slot may be configured to reduce the potential of being able to withdraw a transdermal patch back out of the containment through the patch disposal slot. The interior of the containment may include one or more ribs which may reduce the potential of being able to withdraw a transdermal patch back out of the containment through the patch disposal slot.

Abstract: A multiconfigurable integrated circuit having volatile and nonvolatile segments configured and interconnected so that data can be nonvolatilely entered and transferred at high frequency in the volatile segment, so that formerly entered data can be nonvolatilely stored while new data is entered and volatiley utilized, and so that previously stored nonvolatile data can be recalled and volatilely utilized. In one form, the circuit is comprised of a shift register stage selectively connectable to a nonvolatile memory cell structure. Interconnection of multiple circuits and the addition of analog switches creates electronic equivalents of DIP switches and various other multiple pole selectively controlled switching configurations.

Abstract: The circuit and structure of a direct write differential nonvolatile memory cell. The features of the cell include high speed read sensing, write without a prior erase operation, single polysilicon fabrication capability, and memory margining capabilities. The structural and functional symmetry maximizes cell density while providing complementary differential operation. In a preferred arrangement, the cell utilizes a pair of cross-coupled, capacitively complementary, centrally disposed floating gate electrodes. The cell is written directly by the provision of complementary signals on a pair of program lines, which lines are capacitively coupled to the floating gate electrodes. The data state of the cell is sensed by conduction in two bit lines, the conductive states of the lines being determined by the charge transferred onto the two floating gate electrodes during the simultaneous but complementary programming of such electrodes.

Abstract: A floating gate type nonvolatile memory cell of the general class known as electrically erasable programmable read only memories, configured with a single polysilicon layer, operable in a direct write mode, and characterized by its absence of read disturb. In one form of its practice, the floating gate is divided into three regions situated with relation to specified regions in the substrate. The first region of the floating gate is dielectrically isolated from a conductively doped region in the substrate so as to form a capacitor; the second region is similarly situated, but forms a significantly smaller capacitor and utilizes a dielectric suitable for Fowler-Nordheim tunneling or Poole-Frenkel conduction of charge therethrough; and the third region overlaps a channel of a field effect type sense transistor, conduction through which is responsive to the charge resident on the floating gate.

Abstract: An EEPROM cell which is programmed to a 1 or .0. binary state regardless of the prior state of the cell, that is, without erasing. The cell construction includes silicon nitride capacitors between the floating gate and the programming electrodes which enhances the programming characteristics and the endurance and permits the use of a relatively simple double layer polysilicon process and semiconductor structure.

Abstract: Disclosed is an on-chip, dual polarity high voltage multiplier circuit consisting of a main high positive voltage multiplier and high negative voltage multiplier and an auxiliary high negative voltage multiplier coupled to the main multipliers to prevent turning on of parasitic transistors associated with the MOS diodes of the main multipliers and thereby extend the operating temperature range to 150.degree. C. and improve the fall time of the dual polarity multiplier. The auxiliary multiplier may be located in a common p-well with the main positive and negative multipliers or with the main negative multiplier and its output voltage is connected to this common well.

Abstract: A process for forming zener diodes from an IC structure having coextensive layers of gate silicon dioxide and polycrystalline silicon on a substrate and self-aligned with a diffused region in the substrate. A differential oxidation of the polycrystalline silicon and substrate silicon is followed in turn by a silicon dioxide etch to expose only the polycrystalline silicon layer. Thereafter, the exposed polycrystalline silicon is etched with an etchant that does not materially etch silicon dioxide. The exposed substrate is then subjected to an ion implantation, performed with an energy sufficient to locate the peak impurity concentration below the substrate surface, and a dose sufficient to moderately dope the area originally under the polycrystalline silicon electrode while reducing the effective concentration of the opposite impurity type dopant in the diffused region of the substrate.

Abstract: A process for fabricating an electrical contact which connects an epitaxial layer, well, or substrate with a metallic interconnect layer during the course of creating active integrated circuit devices in a semiconductor wafer. The process forms self-aligned contacts by establishing the contact locations coincident with the definition of the active regions, at an early step in the wafer fabrication process. Thereafter, a gate silicon dioxide layer and a polycrystalline silicon electrode layer are combined to mask the contact region surface from intermediate process environments, e.g., ion implantation and POCl.sub.3 diffusion operations. As the wafer fabrication process approaches conclusion, the contact region is opened by a selective etch of the polycrystalline silicon and the silicon dioxide layers, an enhancement implant into the surface of the contact region, a hydrogen environment annealing operation, and a deposition and patterning of the metallic interconnect layer.

Abstract: Disclosed is a process which is fully compatible with normal two layer polysilicon SNOS process and provides polysilicon parallel plate capacitors and silicon gate non-memory MOS transistors (diodes) for constructing therefrom an on-chip, dual polarity high voltage multiplier. From the polysilicon I layer deposited over a gate oxide, the polysilicon I resistor, the non-memory device gate and the capacitor lower plate are formed. Then, the resistor, non-memory device gate and active region and the periphery of the capacitor lower plate are covered with an isolation oxide. Next, a dielectric, e.g., oxide-nitride, and polysilicon II layers are formed over the structure. Polysilicon II is patterned into interconnect, gate for SNOS memory device and capacitor upper plate, the latter having a plurality of holes therein. The dielectric is formed into SNOS device gate insulator and the capacitor insulator, the latter having holes in registration with the holes in the capacitor upper plate.