Patents by Inventor James A. Tornello
James A. Tornello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262866Abstract: A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas.Type: GrantFiled: January 29, 2018Date of Patent: April 16, 2019Assignees: International Business Machines Corporation, JSR CORPORATIONInventors: Henry A. Beveridge, Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Publication number: 20180166292Abstract: A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas.Type: ApplicationFiled: January 29, 2018Publication date: June 14, 2018Inventors: Henry A. Beveridge, Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Patent number: 9916985Abstract: A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas.Type: GrantFiled: May 20, 2016Date of Patent: March 13, 2018Assignees: International Business Machines Corporation, JSR CORPORATIONInventors: Henry A. Beveridge, Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Patent number: 9890300Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.Type: GrantFiled: April 18, 2017Date of Patent: February 13, 2018Assignees: International Business Machines Corporation, JSR CorporationInventors: Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Publication number: 20170218229Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Inventors: Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Patent number: 9646841Abstract: A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.Type: GrantFiled: May 20, 2016Date of Patent: May 9, 2017Assignees: International Business Machines Corporation, JSR CorporationInventors: Henry A. Beveridge, Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Patent number: 9646842Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.Type: GrantFiled: May 20, 2016Date of Patent: May 9, 2017Assignees: International Business Machines Corporation, JSR CORPORATIONInventors: Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Publication number: 20170110334Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.Type: ApplicationFiled: May 20, 2016Publication date: April 20, 2017Inventors: Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Publication number: 20170110332Abstract: A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas.Type: ApplicationFiled: May 20, 2016Publication date: April 20, 2017Inventors: Henry A. Beveridge, Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Publication number: 20170110333Abstract: A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.Type: ApplicationFiled: May 20, 2016Publication date: April 20, 2017Inventors: Henry A. Beveridge, Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
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Patent number: 8263497Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.Type: GrantFiled: January 13, 2009Date of Patent: September 11, 2012Assignee: International Business Machines CorporationInventors: Paul S. Andry, John M. Cotte, Michael F. Lofaro, Edmund J. Sprogis, James A. Tornello, Cornelia K. Tsang
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Patent number: 7955160Abstract: A glass mold polishing structure and method. The method includes providing a polishing tool comprising mounting plate, a chuck plate over and mechanically attached to the mounting plate, and a pad structure over and mechanically attached to the chuck plate. A retaining structure is attached the chuck plate. A glass mold comprising a plurality of cavities is placed on the pad structure and within a perimeter formed by the retaining structure. A vacuum device is attached to the chuck plate. The vacuum device is activated such that a vacuum is formed and mechanically attaches the glass mold to the pad structure. The polishing tool comprising the glass mold mechanically attached to the pad structure is placed over and in contact with the polishing pad. The polishing tool comprising the glass mold is rotated. The glass mold is polished as a result of the rotation.Type: GrantFiled: June 9, 2008Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Michael A. Cobb, Dinesh R. Koli, Michael F. Lofaro, Dennis G. Manzer, Paraneetha Poloju, James A. Tornello
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Publication number: 20100178766Abstract: An assembly including a main wafer having a body with a front side and a back side, and a handler wafer, is obtained. The main wafer has a plurality of blind electrical vias terminating above the back side. The blind electrical vias have conductive cores with surrounding insulator adjacent side and end regions of the cores. The handler wafer is secured to the front side of the body of the main wafer. An additional step includes exposing the blind electrical vias on the back side. The blind electrical vias are exposed to various heights across the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer.Type: ApplicationFiled: January 13, 2009Publication date: July 15, 2010Applicant: International Business Machines CorporationInventors: Paul S. Andry, John M. Cotte, Michael F. Lofaro, Edmund J. Sprogis, James A. Tornello, Cornelia K. Tsang
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Publication number: 20090305616Abstract: A glass mold polishing structure and method. The method includes providing a polishing tool comprising mounting plate, a chuck plate over and mechanically attached to the mounting plate, and a pad structure over and mechanically attached to the chuck plate. A retaining structure is attached the chuck plate. A glass mold comprising a plurality of cavities is placed on the pad structure and within a perimeter formed by the retaining structure. A vacuum device is attached to the chuck plate. The vacuum device is activated such that a vacuum is formed and mechanically attaches the glass mold to the pad structure. The polishing tool comprising the glass mold mechanically attached to the pad structure is placed over and in contact with the polishing pad. The polishing tool comprising the glass mold is rotated. The glass mold is polished as a result of the rotation.Type: ApplicationFiled: June 9, 2008Publication date: December 10, 2009Inventors: Michael A. Cobb, Dinesh R. Koli, Michael F. Lofaro, Dennis G. Manzer, Praneetha Poloju, James A. Tornello
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Patent number: 7581314Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.Type: GrantFiled: February 21, 2006Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
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Patent number: 7202764Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.Type: GrantFiled: July 8, 2003Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
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Patent number: 7199450Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.Type: GrantFiled: May 13, 2005Date of Patent: April 3, 2007Assignee: International Business Machines CorporationInventors: Jon A. Casey, Michael Berger, Leena P. Buchwalter, Donald F. Canaperi, Raymond R. Horton, Anurag Jain, Eric D. Perfecto, James A. Tornello
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Publication number: 20030073593Abstract: Slurry compositions comprising an oxidizing agent, optionally a copper corrosion inhibitor, abrasive particles; surface active agent, a service of chloride and a source of sulfate ions.Type: ApplicationFiled: August 30, 2002Publication date: April 17, 2003Inventors: Michael Todd Brigham, Donald Francis Canaperi, Michael A. Cobb, William Cote, Kenneth M. Davis, Scott Alan Estes, Edward Jack Gordon, James Willard Hannah, Mahadevaiyer Krishnan, Michael F. Lofaro, Michael Joseph MacDonald, Dean Allen Schaffer, George James Slusser, James A. Tornello, Eric Jeffrey White
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Patent number: 6503834Abstract: The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.Type: GrantFiled: October 3, 2000Date of Patent: January 7, 2003Assignee: International Business Machines Corp.Inventors: Xiaomeng Chen, Mahadevaiyer Krishnan, Judith M. Rubino, Carlos J. Sambucetti, Soon-Cheon Seo, James A. Tornello
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Patent number: 6361402Abstract: A method for polishing an object having a layer of photoresist, the method, employing the following steps: a) applying a layer of slurry on an a layer of photoresist on an object having a first and a second side, the layer of photoresist on one of the first and second side, the object having a center axis perpendicular to the first and second side; b) contacting the layer of slurry with a pad having a first and second side, the first side of the pad exerting a force on the slurry.Type: GrantFiled: October 26, 1999Date of Patent: March 26, 2002Assignee: International Business Machines CorporationInventors: Donald F. Canaperi, Rangarajan Jagannathan, Mahadevaiyer Krishnan, Max G. Levy, Uma Satyendra, Matthew Sendelbach, James A. Tornello, William Wille