Abstract: A method of making a waveguiding optical component includes processing a polymer optical material to form a billet having an axis of light transmission and having residual stress maintaining a transverse extent of the billet; placing the billet into a mold, the mold being configured to constrain transverse expansion of the billet according to a desired shape of the waveguiding optical component; and heating the billet in the mold to induce relaxation of the residual stress and corresponding transverse expansion of the billet, thereby forming the billet into the waveguiding optical component with the desired shape. An alternative method begins with a collection of individual canes or fiber segments which are fused during the heating process, bypassing a separate process of forming a billet.

Abstract: A method of making a transverse Anderson localization (TAL) element includes mixing pellets together to make a mixture, the pellets being of two or more distinct materials having respective wave speeds effective to provide Anderson guiding. The mixture is fused to make a preform which has respective pellet-size areas of the distinct materials corresponding to the pellets in the mixture. One or more stretching operations is performed to stretch the preform into the TAL element.

Abstract: A method of making a transverse Anderson localization (TAL) element includes mixing pellets together to make a mixture, the pellets being of two or more distinct materials having respective wave speeds effective to provide Anderson guiding. The mixture is fused to make a preform which has respective pellet-size areas of the distinct materials corresponding to the pellets in the mixture. One or more stretching operations is performed to stretch the preform into the TAL element.

Abstract: A method of making a waveguiding optical component includes processing a polymer optical material to form a billet having an axis of light transmission and having residual stress maintaining a transverse extent of the billet; placing the billet into a mold, the mold being configured to constrain transverse expansion of the billet according to a desired shape of the waveguiding optical component; and heating the billet in the mold to induce relaxation of the residual stress and corresponding transverse expansion of the billet, thereby forming the billet into the waveguiding optical component with the desired shape. An alternative method begins with a collection of individual canes or fiber segments which are fused during the heating process, bypassing a separate process of forming a billet.

Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.

Abstract: A wave guide face plate for transmitting an image formed in a scintillating material included as part of a transmitting medium is disclosed. The transmitting medium includes a random distribution of different refractive index regions in two orthogonal dimensions, and an essentially consistent refractive index in a third orthogonal dimension. The third orthogonal direction is aligned with a transmission axis of the wave transmitter extending from an input location to a wave detector location. The transmission efficiency of the wave guide faceplate is improved in situations where the entry angle of the input radiation is different from the axis of the wave transmitter as compared to conventional faceplates.

Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.

Abstract: A wave guide face plate for transmitting an image formed in a scintillating material included as part of a transmitting medium is disclosed. The transmitting medium includes a random distribution of different refractive index regions in two orthogonal dimensions, and an essentially consistent refractive index in a third orthogonal dimension. The third orthogonal direction is aligned with a transmission axis of the wave transmitter extending from an input location to a wave detector location. The transmission efficiency of the wave guide faceplate is improved in situations where the entry angle of the input radiation is different from the axis of the wave transmitter as compared to conventional faceplates.

Abstract: An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.

Abstract: A tool for testing a double data rate (“DDR”) memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. At each timing step during the sweep, several tests may be conducted to check for integrity of functionality. The tool thus generates a pass/fail margin table. The locations of the data strobe transitions selected by the memory controller during its previously run training sequence are then added to this tool-generated margin table. The result is essentially a pseudo data eye, reconstructed including the data strobe transition with the data eye.

Abstract: A data processing system includes a command buffer and control circuitry. The command buffer is configured to store pending write requests to a memory in which each pending write request has corresponding write data. The control circuitry is configured to select a pending write request from an entry of the command buffer and send the selected write request to the memory. The selected write request is a partial write request having first write data stored in the entry. Sending the selected write request includes performing a read-modify-write (RMW), wherein the control circuitry is configured to, after a read operation of the RMW, update the pending write request in the entry from a partial write request to a full write request.

Abstract: A data processing system includes a command buffer and control circuitry. The command buffer is configured to store pending write requests to a memory in which each pending write request has corresponding write data. The control circuitry is configured to select a pending write request from an entry of the command buffer and send the selected write request to the memory. The selected write request is a partial write request having first write data stored in the entry. Sending the selected write request includes performing a read-modify-write (RMW), wherein the control circuitry is configured to, after a read operation of the RMW, update the pending write request in the entry from a partial write request to a full write request.

Abstract: A tool for testing a double data rate (“DDR”) memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. At each timing step during the sweep, several tests may be conducted to check for integrity of functionality. The tool thus generates a pass/fail margin table. The locations of the data strobe transitions selected by the memory controller during its previously run training sequence are then added to this tool-generated margin table. The result is essentially a pseudo data eye, reconstructed including the data strobe transition with the data eye.

Abstract: A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.

Abstract: A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that receives data from a memory. The comparator has a first input coupled to an output of the FIFO, and a second input coupled to receive a calibration pattern. The calibration pattern is predetermined to match with a first portion of data from the FIFO, and is predetermined to not match with a second portion of data from the FIFO. The detection and adjustment circuit detects if a transition from the first portion to the second portion occurs within a predetermined time period. If the transition is not detected within the time period, a timing of the gating signal is adjusted.

Abstract: A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.

Abstract: A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that receives data from a memory. The comparator has a first input coupled to an output of the FIFO, and a second input coupled to receive a calibration pattern. The calibration pattern is predetermined to match with a first portion of data from the FIFO, and is predetermined to not match with a second portion of data from the FIFO. The detection and adjustment circuit detects if a transition from the first portion to the second portion occurs within a predetermined time period. If the transition is not detected within the time period, a timing of the gating signal is adjusted.

Abstract: A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.

Abstract: A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories.

Abstract: Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.