Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

Abstract: Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.

Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.

Abstract: A method for generating transposed image data for use in an imaging apparatus having access to a memory includes (a) generating a set of data blocks corresponding to at least a portion of image data representing an image to be printed; (b) performing a combined format and transpose operation on the set of data blocks; and (c) storing a result of the combined format and transpose operation in the memory.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract: Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.

Abstract: Error diffusion is performed upon input image data. In one aspect, multiple error diffusion processing elements perform error diffusion on a selected pixel in parallel. In another aspect, the error diffusion logic is integrally formed with a fast local memory in the same electronic device, such as an ASIC. The error data produced by the error diffusion logic for a pixel is buffered in the fast local memory until it is to be used by the error diffusion logic on other pixels. In still another aspect, a first-in-first-out (FIFO) buffer regulates or buffers the color image data between the output of a color conversion system, such as a colorant lookup table, and the input an error diffusion processing element. In yet another aspect, the error diffusion logic has tagging logic that produces and stores an indicator, either in the output data stream itself or in a separate area, to indicate whether a raster contains printable data.

Abstract: A method for generating transposed image data for use in an imaging apparatus having access to a memory includes (a) generating a set of data blocks corresponding to at least a portion of image data representing an image to be printed; (b) performing a combined format and transpose operation on the set of data blocks; and (c) storing a result of the combined format and transpose operation in the memory.

Abstract: A stand-alone printing apparatus for transferring one or more digital photographs captured by a digital device to a printable medium. The printing apparatus includes an input member for receiving the digital photographs from a source and image processing for generating an image corresponding to each of the digital photographs. A graphical user interface with video display is integrated within the printing apparatus and includes a plurality of different states in which to preview the digital photograph images, select photographs for printing, and preview a printed page of selected photographs.

Abstract: The present invention is directed to systems and methods for formatting hardware for a printhead, for use in a printing device. The systems and methods of the present invention can support the formatting function with hardware formatting logic. This hardware formatting logic can support multiple printhead platforms. The hardware formatting logic of the present invention can perform bit shifting, resolution reduction, bit per pixel reduction, data masking for shingling, and input data sourcing. The present invention can also include a system processor further including an embedded ARM processor which can fetch and execute instructions and/or firmware. These instructions can direct the embedded processor to configure a format block included within the system processor. The format block can be configured by the system processor via one or more control registers.

Abstract: Error diffusion is performed upon input image data. In one aspect, multiple error diffusion processing elements perform error diffusion on a selected pixel in parallel. In another aspect, the error diffusion logic is integrally formed with a fast local memory in the same electronic device, such as an ASIC. The error data produced by the error diffusion logic for a pixel is buffered in the fast local memory until it is to be used by the error diffusion logic on other pixels. In still another aspect, a first-in-first-out (FIFO) buffer regulates or buffers the color image data between the output of a color conversion system, such as a colorant lookup table, and the input an error diffusion processing element. In yet another aspect, the error diffusion logic has tagging logic that produces and stores an indicator, either in the output data stream itself or in a separate area, to indicate whether a raster contains printable data.

Abstract: The present invention is directed to systems and methods for formatting hardware for a printhead, for use in a printing device. The systems and methods of the present invention can support the formatting function with hardware formatting logic. This hardware formatting logic can support multiple printhead platforms. The hardware formatting logic of the present invention can perform bit shifting, resolution reduction, bit per pixel reduction, data masking for shingling, and input data sourcing. The present invention can also include a system processor further including an embedded ARM processor which can fetch and execute instructions and/or firmware. These instructions can direct the embedded processor to configure a format block included within the system processor. The format block can be configured by the system processor via one or more control registers.