Patents by Inventor James Albert Kirchgessner

James Albert Kirchgessner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132093
    Abstract: A transistor with an emitter, base, and collector. The base includes a monocrystalline base layer. A sacrificial material is formed on the monocrystalline base layer. The sacrificial material is removed to expose a portion of the monocrystalline base layer. A base silicide includes a portion formed on the portion of the base monocrystalline base layer that was exposed by the removal of the sacrificial material.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 29, 2024
    Assignee: NXP USA, Inc.
    Inventors: Ljubo Radic, Ronald Willem Arnoud Werkman, James Albert Kirchgessner, Jay Paul John
  • Publication number: 20240304707
    Abstract: Disclosed is a SiGe, HBT, and method of manufacturing the same, comprising: an n-doped buried collector; a p-doped SiGe base layer, within a layer stack, the layer stack being over and in direct contact with the collector; an n-doped monocrystalline silicon emitter; an epitaxial silicon base contact layer over a second area of the layer stack; a polycrystalline silicon emitter contact layer; an oxide layer over a third area of the layer stack between the first and second areas, wherein the oxide layer and the n-doped monocrystalline silicon emitter are within a window, having sidewalls, in the epitaxial silicon layer; dielectric spacers on the sidewalls of the window and over the oxide layer, and providing electrical isolation between the epitaxial silicon layer and the polycrystalline silicon layer; the epitaxial silicon layer extending beneath the dielectric spacers on the sidewalls of the window.
    Type: Application
    Filed: March 5, 2024
    Publication date: September 12, 2024
    Inventors: Johannes Josephus Theodorus Marinus Donkers, Jay Paul John, James Albert Kirchgessner, Patrick Sebel
  • Publication number: 20240234552
    Abstract: Disclosed is a method of manufacturing a silicon bipolar junction transistor device, the method comprising a sequence of steps including: depositing a polysilicon layer over at least a device region; depositing a dielectric layer over the polysilicon layer; patterning a photoresist layer and etching a window in the dielectric layer and the polysilicon layer through an opening in the photoresist layer; etching a SiGe layer stack through the window, to expose a silicon layer thereunder; patterning a further photoresist layer to expose at least the window; and doping the silicon layer by ion implantation through the window to form a base region. A corresponding BJT device is also disclosed.
    Type: Application
    Filed: December 4, 2023
    Publication date: July 11, 2024
    Inventors: Jay Paul John, Patrick Sebel, James Albert Kirchgessner
  • Publication number: 20240204052
    Abstract: A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Inventors: Jay Paul John, James Albert Kirchgessner
  • Publication number: 20240204086
    Abstract: A semiconductor device includes a semiconductor substrate, a collector region having a first width formed within the semiconductor substrate and an intrinsic base region having a second width, disposed over the collector region, wherein the first width is greater than the second width. An extrinsic base region having an upper surface is formed over the collector region and electrically coupled to the intrinsic base region, wherein the extrinsic base region includes a monocrystalline region coupled to the intrinsic base region and a polycrystalline region coupled to the monocrystalline region. An emitter region is formed over the base region.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 20, 2024
    Inventors: Jay Paul John, James Albert Kirchgessner, Johannes Josephus Theodorus Marinus Donkers, Ljubo Radic
  • Publication number: 20240178304
    Abstract: A semiconductor device includes a semiconductor substrate, a collector region formed within the semiconductor substrate in a first semiconductor region having an upper surface and a collector sidewall, a base region disposed over the collector region, a seed region formed over the semiconductor substrate and coupled to the semiconductor substrate outside the base region, an extrinsic base region having an upper surface and formed over the seed region and electrically coupled to the base region, and an emitter region formed over the base region.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Ljubo Radic, Jay Paul John, James Albert Kirchgessner, Johannes Josephus Theodorus Marinus Donkers
  • Publication number: 20240079473
    Abstract: A method for forming a transistor with an emitter, intrinsic base, and collector. The base includes a semiconductor layer doped with a conductivity dopant to provide for a lower resistivity path to the intrinsic base. After the formation of a layer over a substrate, an emitter window opening is formed in the layer. The semiconductor layer is formed through the opening by a deposition process. A portion of the semiconductor layer is then removed. An emitter electrode is formed that includes at least a portion located in the opening. A remaining portion of the semiconductor layer is in a conductive path to the intrinsic base.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Jay Paul John, James Albert Kirchgessner, Ljubo Radic, Johannes Josephus Theodorus Marinus Donkers
  • Patent number: 11855173
    Abstract: A semiconductor die includes a transistor with an emitter, base, and collector. The base includes an intrinsic base that is located in monocrystalline semiconductor material grown in an opening of a first semiconductor layer. A second semiconductor layer is located above the first semiconductor layer and includes a monocrystalline portion. In some embodiments, an opening was formed in the second semiconductor layer wherein a portion of the underlying first semiconductor layer was etched to form a cavity in which a monocrystalline intrinsic base was grown.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: December 26, 2023
    Assignee: NXP USA, INC.
    Inventors: Jay Paul John, Ljubo Radic, James Albert Kirchgessner, Johannes Josephus Theodorus Marinus Donkers
  • Publication number: 20230395692
    Abstract: A transistor with an emitter, base, and collector. The base includes a monocrystalline base layer. A sacrificial material is formed on the monocrystalline base layer. The sacrificial material is removed to expose a portion of the monocrystalline base layer. A base silicide includes a portion formed on the portion of the base monocrystalline base layer that was exposed by the removal of the sacrificial material.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Ljubo Radic, Ronald Willem Arnoud Werkman, James Albert Kirchgessner, Jay Paul John
  • Patent number: 11817486
    Abstract: A semiconductor device and a method of making a semiconductor device are described. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: November 14, 2023
    Assignee: NXP USA, Inc.
    Inventors: James Albert Kirchgessner, Jay Paul John, Steven Kwan
  • Publication number: 20230187527
    Abstract: A semiconductor die includes a transistor with an emitter, base, and collector. The base includes an intrinsic base that is located in monocrystalline semiconductor material grown in an opening of a first semiconductor layer. A second semiconductor layer is located above the first semiconductor layer and includes a monocrystalline portion. In some embodiments, an opening was formed in the second semiconductor layer wherein a portion of the underlying first semiconductor layer was etched to form a cavity in which a monocrystalline intrinsic base was grown.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 15, 2023
    Inventors: Jay Paul John, Ljubo Radic, James Albert Kirchgessner, Johannes Josephus Theodorus Marinus Donkers
  • Patent number: 11640975
    Abstract: A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: May 2, 2023
    Assignee: NXP USA, INC.
    Inventors: Jay Paul John, James Albert Kirchgessner, Ljubo Radic
  • Publication number: 20230131166
    Abstract: A semiconductor device and a method of making a semiconductor device are described. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.
    Type: Application
    Filed: December 26, 2022
    Publication date: April 27, 2023
    Inventors: James Albert Kirchgessner, Jay Paul John, Steven Kwan
  • Patent number: 11569357
    Abstract: A semiconductor device and a method of making a semiconductor device. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 31, 2023
    Assignee: NXP USA, Inc.
    Inventors: James Albert Kirchgessner, Jay Paul John, Steven Kwan
  • Publication number: 20220406906
    Abstract: A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Jay Paul John, James Albert Kirchgessner, Ljubo Radic
  • Publication number: 20220367650
    Abstract: A semiconductor device and a method of making a semiconductor device. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Inventors: James Albert Kirchgessner, Jay Paul John, Steven Kwan
  • Patent number: 11018247
    Abstract: A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: May 25, 2021
    Assignee: NXP USA, Inc.
    Inventors: Ljubo Radic, Jay Paul John, Bernhard Grote, James Albert Kirchgessner
  • Patent number: 10763782
    Abstract: A technique for tuning a ladder-shaped inductor that achieves a finer tuning resolution by severing one or more shorts, skipping the severing of one or more shorts, and severing one or more subsequent shorts within the ladder-shaped inductor. This technique can be applied to a voltage-controlled oscillator using a differential or single-ended ladder-shaped inductor as part of the resonant circuit. Within an oscillator, such a technique provides for a more precise modulation of the effective inductance of the ladder-shaped inductor, which enables an improved tuning resolution of the operating frequency of the oscillator.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 1, 2020
    Assignee: NXP USA, INC.
    Inventors: Kun-Hin To, David Gareth Morgan, Jay Paul John, James Albert Kirchgessner
  • Patent number: 10269943
    Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 23, 2019
    Assignee: NXP USA, INC.
    Inventors: Jay Paul John, Vishal Trivedi, James Albert Kirchgessner
  • Publication number: 20180102421
    Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.
    Type: Application
    Filed: August 14, 2017
    Publication date: April 12, 2018
    Inventors: JAY PAUL JOHN, VISHAL TRIVEDI, JAMES ALBERT KIRCHGESSNER