Patents by Inventor James Allen Teplik
James Allen Teplik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11784236Abstract: Methods of fabricating a semiconductor device include providing a semiconductor substrate that includes a plurality of epitaxial layers, including a channel layer and a permanent cap over the channel layer, where the permanent cap defines an upper surface of the semiconductor substrate, and forming a sacrificial cap over the permanent cap in an active region of the device, where the sacrificial cap comprises a semiconductor material that includes aluminum. The method also includes forming one or more current carrying regions (e.g., source and drain regions) in the semiconductor substrate in the active region of the device by performing an ion implantation process to implant ions through the sacrificial cap, and into the semiconductor substrate, completely removing the sacrificial cap in the active region of the device, while refraining from removing the permanent cap, and forming one or more current carrying contacts over the one or more current carrying regions.Type: GrantFiled: September 29, 2020Date of Patent: October 10, 2023Assignee: NXP USA, Inc.Inventors: Jenn Hwa Huang, Yuanzheng Yue, Bruce Mcrae Green, Karen Elizabeth Moore, James Allen Teplik
-
Patent number: 11437301Abstract: A device includes a substrate, an insulating layer that includes an etch stop layer formed over an upper surface of the substrate, a first conductive region formed over the insulating layer, and an opening formed within the substrate that extends from a lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region. A method for forming the device includes forming the substrate, forming the insulating layer that includes the etch stop layer over the upper surface of the substrate, forming a first conductive region over the insulating layer; and forming an opening within the substrate that extends from the lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region formed over the insulating layer.Type: GrantFiled: October 15, 2020Date of Patent: September 6, 2022Assignee: NXP USA, Inc.Inventors: Yuanzheng Yue, James Allen Teplik, Bruce McRae Green, Fred Reece Clayton
-
Publication number: 20220122903Abstract: A device includes a substrate, an insulating layer that includes an etch stop layer formed over an upper surface of the substrate, a first conductive region formed over the insulating layer, and an opening formed within the substrate that extends from a lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region. A method for forming the device includes forming the substrate, forming the insulating layer that includes the etch stop layer over the upper surface of the substrate, forming a first conductive region over the insulating layer; and forming an opening within the substrate that extends from the lower surface of the substrate, through the upper surface of the substrate, and through at least a portion the insulating layer, terminating on the first conductive region formed over the insulating layer.Type: ApplicationFiled: October 15, 2020Publication date: April 21, 2022Inventors: Yuanzheng Yue, James Allen Teplik, Bruce McRae Green, Fred Reece Clayton
-
Publication number: 20220102529Abstract: Methods of fabricating a semiconductor device include providing a semiconductor substrate that includes a plurality of epitaxial layers, including a channel layer and a permanent cap over the channel layer, where the permanent cap defines an upper surface of the semiconductor substrate, and forming a sacrificial cap over the permanent cap in an active region of the device, where the sacrificial cap comprises a semiconductor material that includes aluminum. The method also includes forming one or more current carrying regions (e.g., source and drain regions) in the semiconductor substrate in the active region of the device by performing an ion implantation process to implant ions through the sacrificial cap, and into the semiconductor substrate, completely removing the sacrificial cap in the active region of the device, while refraining from removing the permanent cap, and forming one or more current carrying contacts over the one or more current carrying regions.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Inventors: Jenn Hwa Huang, Yuanzheng Yue, Bruce McRae Green, Karen Elizabeth Moore, James Allen Teplik
-
Patent number: 10971613Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: GrantFiled: March 30, 2020Date of Patent: April 6, 2021Assignee: NXP USA, Inc.Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
-
Patent number: 10957790Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: GrantFiled: December 31, 2018Date of Patent: March 23, 2021Assignee: NXP USA, Inc.Inventors: Bruce McRae Green, Darrell Glenn Hill, Karen Elizabeth Moore, Jenn-Hwa Huang, Yuanzheng Yue, James Allen Teplik, Lawrence Scott Klingbeil
-
Patent number: 10741496Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over a semiconductor substrate, a source electrode and a drain electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, a gate electrode formed over the semiconductor substrate between the source electrode and the drain electrode, and a protection layer disposed on the source electrode, the drain electrode, and the first dielectric layer, wherein a first edge of the protection layer terminates the protection layer between the source electrode and the gate electrode, and a second edge of the protection layer terminates the protection layer between the gate electrode and the drain electrode. A method for fabricating the semiconductor devices includes forming a first dielectric layer over the semiconductor substrate, forming source and drain electrodes, depositing the protection layer over the source and drain electrodes, and forming the gate electrode.Type: GrantFiled: December 4, 2018Date of Patent: August 11, 2020Assignee: NXP USA, Inc.Inventors: Jenn Hwa Huang, James Allen Teplik, Darrell Glenn Hill
-
Publication number: 20200227547Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: ApplicationFiled: March 30, 2020Publication date: July 16, 2020Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
-
Publication number: 20200176389Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over a semiconductor substrate, a source electrode and a drain electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, a gate electrode formed over the semiconductor substrate between the source electrode and the drain electrode, and a protection layer disposed on the source electrode, the drain electrode, and the first dielectric layer, wherein a first edge of the protection layer terminates the protection layer between the source electrode and the gate electrode, and a second edge of the protection layer terminates the protection layer between the gate electrode and the drain electrode. A method for fabricating the semiconductor devices includes forming a first dielectric layer over the semiconductor substrate, forming source and drain electrodes, depositing the protection layer over the source and drain electrodes, and forming the gate electrode.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Inventors: Jenn Hwa Huang, James Allen Teplik, Darrell Glenn Hill
-
Patent number: 10644142Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: GrantFiled: December 22, 2017Date of Patent: May 5, 2020Assignee: NXP USA, Inc.Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
-
Publication number: 20190198623Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
-
Publication number: 20190157440Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: ApplicationFiled: December 31, 2018Publication date: May 23, 2019Inventors: Bruce McRae Green, Darrell Glenn Hill, Karen Elizabeth Moore, Jenn-Hwa Huang, Yuanzheng Yue, James Allen Teplik, Lawrence Scott Klingbeil