Patents by Inventor James Andrew Collier A. Scobie
James Andrew Collier A. Scobie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10572261Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.Type: GrantFiled: January 6, 2016Date of Patent: February 25, 2020Assignee: NXP USA, Inc.Inventors: Alistair Paul Robertson, James Andrew Collier Scobie
-
Patent number: 10002057Abstract: A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.Type: GrantFiled: June 3, 2016Date of Patent: June 19, 2018Assignee: NXP USA, Inc.Inventors: James Andrew Collier Scobie, Alan R. Duncan, Alison Young, Alistair P. Robertson
-
Patent number: 9952922Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.Type: GrantFiled: July 18, 2013Date of Patent: April 24, 2018Assignee: NXP USA, Inc.Inventors: Graham Edmiston, Alan Devine, David McMenamin, Andrew Roberston, James Andrew Collier Scobie
-
Publication number: 20180039544Abstract: A resource access management component arranged to manage access to resources within a processing system. The resource access management component comprises at least one resource access management device configurable to manage access to the resources by a plurality of interconnect-master devices of the processing system. The resource access management component further comprises at least one resource access configuration unit arranged to receive an indication when a fault has been detected in relation to an interconnect-master device of the processing system, and to reconfigure the resource access management device in response to receiving the indication that a fault has been detected in relation to the interconnect-master device.Type: ApplicationFiled: July 17, 2017Publication date: February 8, 2018Inventors: JAMES ANDREW COLLIER SCOBIE, David McMenamin
-
Publication number: 20170351577Abstract: A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.Type: ApplicationFiled: June 3, 2016Publication date: December 7, 2017Inventors: James Andrew Collier SCOBIE, Alan R. DUNCAN, Alison YOUNG, Alistair P. ROBERTSON
-
Publication number: 20170192790Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.Type: ApplicationFiled: January 6, 2016Publication date: July 6, 2017Applicant: Freescale Semiconductor, Inc.Inventors: Alistair Paul Robertson, James Andrew Collier Scobie
-
Patent number: 9575911Abstract: An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.Type: GrantFiled: April 7, 2014Date of Patent: February 21, 2017Assignee: NXP USA, INC.Inventors: David McMenamin, James Andrew Collier Scobie
-
Publication number: 20160239362Abstract: Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.Type: ApplicationFiled: July 18, 2013Publication date: August 18, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Graham EDMISTON, Alan DEVINE, David MCMENAMIN, Andrew ROBERTSON, James Andrew Collier SCOBIE
-
Publication number: 20150286595Abstract: An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.Type: ApplicationFiled: April 7, 2014Publication date: October 8, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: DAVID MCMENAMIN, JAMES ANDREW COLLIER SCOBIE
-
Patent number: 8966286Abstract: A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.Type: GrantFiled: January 5, 2009Date of Patent: February 24, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Alistair Robertson, Derek Beattie, James Andrew Collier Scobie
-
Patent number: 8543860Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.Type: GrantFiled: August 26, 2008Date of Patent: September 24, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Derek Beattie, Carl Culshaw, Alan Devine, James Andrew Collier Scobie
-
Publication number: 20130111168Abstract: An electronic system includes multiple data access components (DACs), a semaphores module, and a memory protection unit (MPU). Any of the DACs may issue an access request, which requests access to a shared system resource. A region descriptor associated with the shared system resource specifies default access permissions for the DACs. The semaphores module implements a semaphore for the shared system resource, and produces semaphore signals indicating which one, if any, of the DACs has locked the semaphore for the shared system resource. More particularly, an access evaluation circuit of the MPU receives the default access permissions and the semaphore signals. When the semaphore is properly enabled, as indicated in the region descriptor, the access evaluation circuit produces effective access permissions for the DACs by potentially altering the default access permissions based on the semaphore signals. The MPU grants or denies the access request based on the effective access permissions.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Joseph C. Circello, James Andrew Collier A. Scobie
-
Patent number: 8242815Abstract: A microcontroller unit comprises a reset controller operably coupled to a plurality of logic elements of the microcontroller unit. Low voltage detection logic is operably coupled to the reset controller and arranged to provide a plurality of low voltage interrupt signals to a number of respective logic elements of the microcontroller unit via the reset controller. A method of operating a microcontroller unit is also described.Type: GrantFiled: April 26, 2007Date of Patent: August 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: James Andrew Collier Scobie, Derek Beattie, Carl Culshaw, Alan Devine, James Feddeler
-
Publication number: 20110258462Abstract: A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.Type: ApplicationFiled: January 5, 2009Publication date: October 20, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Alistair Robertson, Derek Beattie, James Andrew Collier Scobie
-
Publication number: 20110145625Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.Type: ApplicationFiled: August 26, 2008Publication date: June 16, 2011Inventors: Derek Beattie, Carl Culshaw, Alan Devine, James Andrew Collier Scobie
-
Publication number: 20110012650Abstract: A microcontroller unit comprises a reset controller operably coupled to a plurality of logic elements of the microcontroller unit. Low voltage detection logic is operably coupled to the reset controller and arranged to provide a plurality of low voltage interrupt signals to a number of respective logic elements of the microcontroller unit via the reset controller. A method of operating a microcontroller unit is also described.Type: ApplicationFiled: April 26, 2007Publication date: January 20, 2011Applicant: Freescale Seminconductor, Inc.Inventors: James Andrew Collier Scobie, Derek Beattie, Carl Culshaw, Alan Devine, James Feddeler