Patents by Inventor James Andrew Davis

James Andrew Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7149949
    Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, a set of test cells in a test row are used to predict failures amongst a set of cells of interest storing a block of ECC encoded data. Erasure information is formed from these predictions which identifies potentially unreliable symbols in the block of ECC encoded data, and the ability of a decoder to perform ECC decoding is substantially enhanced.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: December 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan Jedwab, James Andrew Davis, Gadiel Seroussi
  • Patent number: 7107507
    Abstract: A magnetoresistive solid-state storage device (MRAM device) uses storage cells 16 arranged in many arrays 10 to form a macro-array 2. For fast access times and to reduce exposure to physical failures, each unit of data (e.g. a sector) is stored with a few sub-units (e.g. bytes) in each of a large plurality of the arrays 10. Advantageously, the plurality of arrays 10 are accessible in parallel substantially simultaneously, and a failure in any one array affects only a small portion of the data unit. Optionally, error correction coding (ECC) is employed to form encoded data with symbols which are stored according to preferred embodiments which further minimise exposure to physical failures.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Andrew Davis, Jonathan Jedwab, Stephen Morley, Kenneth Graham Paterson
  • Patent number: 7107508
    Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data. The test comprises identifying failed cells where the failures will be visible in use for the generation of erasure information used in ECC decoding, by comparing parametric values obtained from the cells against one or more failure ranges, and includes performing a write-read-compare operation with test data to identify failed cells which will be hidden for the generation of erasure information in use. A failure count is formed based on both the visible failures and the hidden failures, to determine that the set of cells is suitable for storing ECC encoded data. The failure count is weighted, with hidden failures having a greater weighting than visible failures.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan Jedwab, James Andrew Davis, Kenneth Graham Paterson, Gadiel Seroussi
  • Patent number: 7036068
    Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: April 25, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Andrew Davis, Jonathan Jedwab, David H. McIntyre, Kenneth Graham Paterson, Frederick A Perner, Gadiel Seroussi, Kenneth K Smith, Stewart R. Wyatt
  • Patent number: 6990622
    Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columns 14 of an array of storage cells 16 which are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: January 24, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Andrew Davis, Jonathan Jedwab, Kenneth Graham Paterson, Gadiel Seroussi
  • Patent number: 6973604
    Abstract: A magnetoresistive state-solid state storage device having arrays of magnetoresistive storage cells. Sparing resources such as a plurality of spare rows are allocated to replace rows of storage cells which are affected by physical failures. A count is made for the number of failed rows within each array, and a count is also made of the number of failed rows within a cross-array row set spread across plural arrays. A spare row or rows are allocated by selecting a cross-array row set affected by the highest number of failed rows and therefore most likely to lead to unreliable data storage, and then selecting an array in this cross-array row set having the lowest number of failed rows, and therefore the least competition for sparing resources. The method proceeds iteratively with counts updated as sparing resources are allocated.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: December 6, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Andrew Davis, Jonathan Jedwab
  • Publication number: 20030172339
    Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. A linear error correction block code such as a Reed-Solomon code forms codewords having a plurality of symbols. In almost all cases, a corrected codeword is formed by error correction decoding a read codeword in a standard first decoder arranged to reliably identify and correct up to a predetermined number of failed symbols, or else determine an unrecoverable error. Error correction decoding of the read codeword is then attempted in a stronger second decoder, ideally being a maximum likelihood decoder arranged to form one or more closest corrected codewords.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Inventors: James Andrew Davis, Jonathan Jedwab, Gadiel Seroussi, David Murray Banks, David H. McIntyre, Stewart R. Wyatt
  • Publication number: 20030172329
    Abstract: A magnetoresistive state-solid state storage device comprises many arrays 101-108 of magnetoresistive storage cells 16. Sparing resources such as a plurality of spare rows 120 are allocated to replace rows 12 of storage cells 16 which are affected by physical failures. A count is made for the number of failed rows within each array, and a count is also made of the number of failed rows within a cross-array row set r1-r4 spread across plural arrays. A spare row or rows 120 are allocated by selecting a cross-array row set r1-r4 affected by the highest number of failed rows and therefore most likely to lead to unreliable data storage, and then selecting an array 10 in this cross-array row set having the lowest number of failed rows, and therefore the least competition for sparing resources. The method proceeds iteratively with counts updated as sparing resources are allocated, thereby leaving until last those arrays 10 for which originally there was intense competition for spares.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Inventors: James Andrew Davis, Jonathan Jedwab
  • Publication number: 20030023923
    Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.
    Type: Application
    Filed: July 25, 2001
    Publication date: January 30, 2003
    Inventors: James Andrew Davis, Jonathan Jedwab, David H. McIntyre, Kenneth Graham Paterson, Frederick A. Perner, Gadiel Seroussi, Kenneth K. Smith, Stewart R. Wyatt
  • Publication number: 20030023911
    Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columns 14 of an array of storage cells 16 which are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.
    Type: Application
    Filed: March 8, 2002
    Publication date: January 30, 2003
    Inventors: James Andrew Davis, Jonathan Jedwab, Kenneth Graham Paterson, Gadiel Seroussi
  • Publication number: 20030023927
    Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, a set of test cells 160 in a test row 120 are used to predict failures 163 amongst a set of cells of interest storing a block of ECC encoded data. Erasure information is formed from these predictions which identifies potentially unreliable symbols 206 in the block of ECC encoded data, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.
    Type: Application
    Filed: March 8, 2002
    Publication date: January 30, 2003
    Inventors: Jonathan Jedwab, James Andrew Davis, Gadiel Seroussi
  • Publication number: 20030023926
    Abstract: A magnetoresistive solid-state storage device (MRAM device) uses storage cells 16 arranged in many arrays 10 to form a macro-array 2. For fast access times and to reduce exposure to physical failures, each unit of data (e.g. a sector) is stored with a few sub-units (e.g. bytes) in each of a large plurality of the arrays 10. Advantageously, the plurality of arrays 10 are accessible in parallel substantially simultaneously, and a failure in any one array affects only a small portion of the data unit. Optionally, error correction coding (ECC) is employed to form encoded data with symbols which are stored according to preferred embodiments which further minimise exposure to physical failures.
    Type: Application
    Filed: March 8, 2002
    Publication date: January 30, 2003
    Inventors: James Andrew Davis, Jonathan Jedwab, Stephen Morley, Kenneth Graham Paterson
  • Publication number: 20030023928
    Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the MRAM device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data. The test comprises identifying failed storage cells where the failures will be visible in use for the generation of erasure information used in ECC decoding, suitably by comparing parametric values obtained from the storage cells against one or more failure ranges, and includes performing a write-read-compare operation with test data to identify failed storage cells which will be hidden for the generation of erasure information in use. A failure count is formed based on both the visible failures and the hidden failures, to determine that the set of storage cells is suitable for storing ECC encoded data. Here, the failure count is weighted, with hidden failures having a greater weighting than visible failures.
    Type: Application
    Filed: March 8, 2002
    Publication date: January 30, 2003
    Inventors: Jonathan Jedwab, James Andrew Davis, Kenneth Graham Paterson, Gadiel Seroussi
  • Patent number: 6487258
    Abstract: In a coded orthogonal frequency division multiplex (COFDM) system n-bit data words are encoded as 2m-symbol code words, each symbol having 2j possible values (e.g. j=3 for octary). An efficient decoder for these code words is provided by applying j iterations of the fast Hadamard transform, the input vector for the second and subsequent iterations being derived from the result of the immediately preceding iteration.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: November 26, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Jonathan Jedwab, James Andrew Davis, Kenneth Graham Paterson
  • Patent number: 6373859
    Abstract: In a coded orthogonal frequency division multiplex (COFDM) system n-bit data words are encoded as 2m-symbol code words (binary, quaternary, octary, etc.). The code words are selected for desired low peak-to-mean envelope power ratio (PMEPR) characteristics of transmissions over a COFDM channel, from a set of cosets of a linear sub-code of a code having a specified generator matrix. The code words thus identified by the procedure described can, even for values of m in excess of 3, simultaneously limit the PMEPR to 3 dB, provide specified error control characteristics, be implemented in a feasible manner using analytical circuit techniques (e.g. with combinatorial logic), and include sufficiently many different code words to enable data to be transferred at useful rates. Other selections of code words can be made, enabling a higher maximum PMEPR or a reduced error detection capability to be accepted in order to obtain a higher code rate.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: April 16, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Jonathan Jedwab, James Andrew Davis
  • Patent number: 6119263
    Abstract: A data packet is transmitted by dividing it into sub-packets, for example by distributing successive bytes of the data packet to different sub-packets each containing at most p.sup.n -1 symbols, where p is a prime number, and transmitting the sub-packets along two or more respective paths. CRC checksums are added to the sub-packets, the checksum for each path being generated using a different and respective generator polynomial of degree b. These generator polynomials are selected so that, for arithmetic carried out modulo p, each polynomial has a respective factor of degree at least b-n+1, and the collection of polynomials which are each exactly divisible by all such factors constitutes a BCH code. As a result the system has advantageous properties in respect of error detection and implementation.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: September 12, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Miranda Jane Felicity Mowbray, James Andrew Davis, Kenneth Graham Paterson, Simon Edwin Crouch