Abstract: A signal processor for 1-bit signals comprises a fifth order Delta-Sigma Modulator (DSM) having an input for receiving a 1-bit signal and an output at which a processed 1-bit signal is produced by a quantizer. The quantizer receives a p-bit signal from a series of five signal integration stages. Each stage comprises a first 1-bit multiplier coupled to the input, a second 1-bit multiplier coupled to the output, an adder which sums the outputs of the coefficient multipliers and an integrator which integrates the output of the adder. A final stage comprises a coefficient multiplier and an adder. The adder sums the output of the coefficient multiplier and the output of the integrator of the preceding integration stage. The coefficients are chosen to provide an overall attenuation of the input signal and of the quantization noise produced by the quantizer. Reduction of quantization noise allows several DSMs to be connected in series by preventing the build-up of excess noise, which may compromise stability.

Abstract: A signal processing system in which a differentially quantized digital signal is used, the digital signal having two bits which represent only three values, of which one value (10 or 01) is zero and the other two (11 and 00) values represent a positive value and a negative value respectively.

Abstract: A signal processor for 1-bit signals comprises a fifth order Delta-Sigma Modulator (DSM) having an input 4 for receiving a 1-bit signal and an output 5 at which a processed 1-bit signal is produced by a quantizer Q. The quantizer Q receives a p-bit signal from a series of 5 signal integration stages. Each stage comprises a first 1-bit multiplier An coupled to the input 4, a second 1-bit multiplier Cn coupled to the output 5, an adder 6n which sums the outputs of the coefficient multipliers and an integrator 7n which integrates the output of the adder 6n. A final stage comprises a coefficient multiplier An+1 and an adder 6n+1. The adder 6n+1 sums the output of the coefficient multiplier An+1 and the output of the integrator of the preceding integration stage.

Abstract: A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section 51 which feeds the 1-bit output signal back to the adder 53.